MCP47FVB01 datasheet(28/92 Pages) MICROCHIP

28 / 92 page

MCP47FVBXX

DS20005405A-page 28

 2015 Microchip Technology Inc.

3.1

Positive Power Supply Input (VDD)

VDD is the positive supply voltage input pin. The input

supply voltage is relative to VSS.

The power supply at the VDD pin should be as clean as

possible for a good DAC performance. It is

recommended to use an appropriate bypass capacitor

of about 0.1 µF (ceramic) to ground. An additional

10 µF capacitor (tantalum) in parallel is also

recommended to further attenuate noise present in

application boards.

3.2

Voltage Reference Pin (VREF)

The VREF pin is either an input or an output. When the

DAC’s voltage reference is configured as the VREF pin,

the pin is an input. When the DAC’s voltage reference is

configured as the internal band gap, the pin is an output.

When the DAC’s voltage reference is configured as the

VREF pin, there are two options for this voltage input:

VREF pin voltage buffered or unbuffered. The buffered

option is offered in cases where the external reference

voltage does not have sufficient current capability to not

drop it’s voltage when connected to the internal resistor

ladder circuit.

When the DAC’s voltage reference is configured as the

device VDD, the VREF pin is disconnected from the

internal circuit.

When the DAC’s voltage reference is configured as the

internal band gap, the VREF pin’s drive capability is

minimal, so the output signal should be buffered.

See Section 5.2 “Voltage Reference Selection” and

3.3

Analog Output Voltage Pin (VOUT)

VOUT is the DAC analog voltage output pin. The DAC

output has an output amplifier. The DAC output range is

dependent on the selection of the voltage reference

source (and potential Output Gain selection). These are:

•Device VDD - The full-scale range of the DAC

output is from VSS to approximately VDD.

•VREF pin - The full-scale range of the DAC output

is from VSS to G  VRL, where G is the gain

selection option (1x or 2x).

• Internal Band Gap - The full-scale range of the

DAC output is from VSS to G  (2  VBG), where G

is the gain selection option (1x or 2x).

In Normal mode, the DC impedance of the output pin is

about 1

. In Power-Down mode, the output pin is

internally connected to a known pull-down resistor of

, 100 k, or open. The Power-Down selection bits

settings are shown Register 4-3 (Table 5-5).

3.4

No Connect (NC)

The NC pin is not connected to the device.

3.5

Ground (VSS)

The VSS pin is the device ground reference.

The user must connect the VSS pin to a ground plane

through a low-impedance connection. If an analog

ground path is available in the application PCB (printed

circuit board), it is highly recommended that the VSS pin

be tied to the analog ground path or isolated within an

analog ground plane of the circuit board.

3.6

Latch Pin (LAT)

The LAT pin is used to force the transfer of the DAC

allows DAC outputs to be updated at the same time.

The update of the VRxB:VRxA, PDxB:PDxA, Gx bits

are also controlled by the LAT pin state.

This pin supports the high voltage (VIHH) supported by

the HVC pin of the nonvolatile family device’s

(MCP47FEBXX).

3.7

I2C - Serial Clock Pin (SCL)

The SCL pin is the serial clock pin of the I2C interface.

The MCP47FVBXX’s I2C interface only acts as a slave

and the SCL pin accepts only external serial clocks.

The input data from the Master device is shifted into the

SDA pin on the rising edges of the SCL clock and

output from the device occurs at the falling edges of the

SCL clock. The SCL pin is an open-drain N-channel

driver. Therefore, it needs an external pull-up resistor

from the VDD line to the SCL pin. Refer to Section 6.0

“I2C Serial Interface Module”

for more details of I2C Serial

Interface communication.

3.8

I2C - Serial Data Pin (SDA)

The SDA pin is the serial data pin of the I2C interface.

The SDA pin is used to write or read the DAC registers

and Configuration bits. The SDA pin is an open-drain

N-channel driver. Therefore, it needs an external

pull-up resistor from the VDD line to the SDA pin. Except

for Start and Stop conditions, the data on the SDA pin

must be stable during the high period of the clock. The

high or low state of the SDA pin can only change when

the clock signal on the SCL pin is low. Refer to

Section 6.0 “I2C Serial Interface Module”

for more details

of I2C Serial Interface communication.

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