MCP47FVB01 datasheet(46/92 Pages) MICROCHIP

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MCP47FVBXX

DS20005405A-page 46

 2015 Microchip Technology Inc.

5.6

Power-Down Operation

To allow the application to conserve power when the

DAC operation is not required, three power-down

modes are available. The Power-Down configuration

bits (PD1:PD0) control the power-down operation

(Figure 5-10 and Table 5-5). On devices with multiple

DACs, each DAC’s power-down mode is individually

controllable. All power-down modes do the following:

• Turn off most the DAC module’s internal circuits

(output op amp, resistor ladder,...)

• Op amp output becomes high-impedance to the

VOUT pin

• Disconnects resistor ladder from reference

voltage (VRL)

• Retains the value of the volatile DAC register and

configuration bits

Depending on the selected power-down mode, the

following will occur:

•VOUT pin is switched to one of two resistive pull-

downs (See Table 5-5)

-100 k

 (typical)

-1 k

 (typical)

• Op amp is powered-down and the VOUT pin is

high-impedance.

There is a delay (TPDE) between the PD1:PD0 bits

changing from ‘00’ to either ‘01’, ‘10’ or ‘11’ and the op

amp no longer driving the VOUT output and the pull-

down resistors sinking current.

In any of the power-down modes where the VOUT pin is

not externally connected (sinking or sourcing current),

the power-down current will typically be ~650 nA for a

single-DAC device. As the number of DACs increases,

the device’s power-down current will also increase.

The power-down bits are modified by using a Write

command to the volatile Power-Down register, or a POR

event which forces the volatile Power-Down bits to the

Normal operation state.

Section 7.0 “Device Commands”

describes the I2C

commands for writing the power-down bits. The

commands that can update the volatile PD1:PD0 bits are:

• Write Command (Normal and High-Voltage)

• Read Command (Normal and High-Voltage)

• General Call Reset

• General Call Wake-up

FIGURE 5-10:

VOUT Power-Down Block

Diagram.

Table 5-6 shows the current sources for the DAC based

on the selected source of the DAC’s reference voltage

and if the device is in normal operating mode or one of

the power-down modes.

Note:

The I2C serial interface circuit is not

affected by the Power-Down mode. This

circuit remains active in order to receive

any command that might come from the

I2C master device.

TABLE 5-5:

POWER-DOWN BITS AND

OUTPUT RESISTIVE LOAD

PD1

PD0

Function

Normal operation

 resistor to ground

100 k

 resistor to ground

Open circuit

TABLE 5-6:

DAC CURRENT SOURCES

Device VDD

Current

Source

PD1:0 = ‘00’,

VREF1:0 =

PD1:0

 ‘00’,

VREF1:0 =

Output

Op Amp

Resistor

Ladder

N (1)

YNN

N (1)

RL Op Amp

Band Gap

Note 1:

Current is sourced from the VREF pin, not the

device VDD.

Gain (1)

V OUT

PD1:PD0

V DD

PD1:PD0

Note 1: Gain options are 1x and 2x.

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