MCP47FVB01 datasheet(81/92 Pages) MICROCHIP

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DS20005405A-page 81

MCP47FVBXX

B.3.4

SLOPE CONTROL

As the device transitions from HS mode to FS mode,

the slope control parameter will change from the HS

specification to the FS specification.

For Fast (FS) and High-Speed (HS) modes, the device

has a spike suppression and a Schmitt Trigger at SDA

and SCL inputs.

B.3.5

DEVICE ADDRESSING

The I2C Slave Address control byte is the first byte

received following the Start condition from the master

device. This byte has 7-bits to specify the Slave

Address and the Read/Write control bit.

Figure B-9 shows the I2C slave address byte format,

which contains the seven address bits and a read/write

(R/W) bit.

FIGURE B-9:

I2C Slave Address Control

Byte.

B.3.6

HS MODE

The I2C specification requires that a High-Speed mode

device must be ‘activated’ to operate in High-Speed

(3.4 Mbit/s) mode. This is done by the master sending

a special address byte following the Start bit. This byte

is referred to as the High-Speed Master Mode Code

(HSMMC).

The device can now communicate at up to 3.4 Mbit/s

on SDA and SCL lines. The device will switch out of the

HS mode on the next Stop condition.

The master code is sent as follows:

Start condition (S)

High-Speed Master Mode Code (0000 1XXX),

The XXX bits are unique to the High-Speed (HS)

mode master.

No Acknowledge (A)

After switching to High-Speed mode, the next

transferred byte is the I2C control byte, which specifies

the device to communicate with, and any number of

data bytes plus acknowledgments. The master device

can then either issue a Repeated Start bit to address a

different device (at High-Speed) or a Stop bit to return

to Fast/Standard bus speed. After the Stop bit, any

other master device (in a multi-master system) can

arbitrate for the I2C bus.

See Figure B-10 for illustration of HS mode command

sequence.

For more information on the HS mode, or other I2C

modes, please refer to the NXP I2C specification.

B.3.6.1

Slope Control

The slope control on the SDA output is different

between the Fast/Standard Speed and the High-Speed

clock modes of the interface.

B.3.6.2

Pulse Gobbler

The pulse gobbler on the SCL pin is automatically

adjusted to suppress spikes < 10 ns during HS mode.

FIGURE B-10:

HS Mode Sequence.

Start bit

Read/Write bit

Address Byte

R/W ACK

Acknowledge bit

7-bit Slave Address

‘0 0 0 0 1 X X X’b

‘Slave Address’

A/A

“Data”

S = Start bit

Sr = Repeated Start bit

A = Acknowledge bit

A = Not Acknowledge bit

R/W = Read/Write bit

R/W

P = Stop bit (Stop condition terminates HS Mode)

F/S-mode

HS-mode

HS-mode continues

F/S-mode

‘Slave Address’ R/W

HS Select Byte

Control Byte

Command/Data Byte(s)

Control Byte

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