MCP47FVB01 datasheet(69/92 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS20005405A-page 69

MCP47FVBXX

8.10.2

LAYOUT CONSIDERATIONS

Several layout considerations may be applicable to

your application. These may include:

• Noise

• PCB Area Requirements

8.10.2.1

Noise

Inductively-coupled AC transients and digital switching

noise can degrade the input and output signal integrity,

potentially masking the MCP47FVBXX’s performance.

Careful board layout minimizes these effects and

increases the Signal-to-Noise Ratio (SNR). Multi-layer

boards utilizing a low-inductance ground plane,

isolated inputs, isolated outputs and proper decoupling

are critical to achieving the performance that the silicon

capable

providing.

Particularly

harsh

environments may require shielding of critical signals.

Separate digital and analog ground planes are

recommended. In this case, the VSS pin and the ground

pins of the VDD capacitors should be terminated to the

analog ground plane.

8.10.2.2

PCB Area Requirements

In some applications, PCB area is a criteria for device

selection. Table 8-2 shows the typical package

dimensions and area for the different package options.

Note:

Breadboards and wire-wrapped boards

are not recommended.

TABLE 8-2:

PACKAGE FOOTPRINT(1)

Package

Package Footprint

Type

Code

Dimensions

(mm)

Area (mm2)

Length Width

TSSOP

3.00

4.40

13.20

Note 1:

Does not include recommended land

pattern dimensions. Dimensions are

typical values.

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