MCP47FVB01 datasheet(68/92 Pages) MICROCHIP

68 / 92 page

MCP47FVBXX

DS20005405A-page 68

 2015 Microchip Technology Inc.

8.9

Software I2C Interface Reset

Sequence

At times, it may become necessary to perform a

Software Reset Sequence to ensure the MCP47FVBXX

device is in a correct and known I2C interface state. This

technique only resets the I2C state machine.

This is useful if the MCP47FVBXX device powers-up in

an incorrect state (due to excessive bus noise, etc), or

if the master device is reset during communication.

Figure 8-9 shows the communication sequence to

software reset the device.

FIGURE 8-9:

Software Reset Sequence

Format.

The 1st Start bit will cause the device to reset from a

state in which it is expecting to receive data from the

master device. In this mode, the device is monitoring

the data bus in Receive mode and can detect if the

Start bit forces an internal Reset.

The nine bits of ‘1’ are used to force a Reset of those

devices that could not be reset by the previous Start bit.

This occurs only if the MCP47FVBXX is driving an A bit

on the I2C bus, or is in Output mode (from a Read

command) and is driving a data bit of ‘0’ onto the I2C

bus. In both of these cases, the previous Start bit could

not be generated due to the MCP47FVBXX holding the

bus low. By sending out nine ‘1’ bits, it is ensured that

the device will see an A bit (the master device does not

drive the I2C bus low to acknowledge the data sent by

the

MCP47FVBXX),

which

also

forces

the

MCP47FVBXX to reset.

The 2nd Start bit is sent to address the rare possibility

of an erroneous write. This could occur if the master

device was reset while sending a Write command to the

MCP47FVBXX, AND then as the master device returns

to normal operation and issues a Start condition, while

the MCP47FVBXX is issuing an acknowledge. In this

case, if the 2nd Start bit is not sent (and the Stop bit was

sent) the MCP47FVBXX could initiate a write cycle.

The Stop bit terminates the current I2C bus activity. The

MCP47FVBXX waits to detect the next Start condition.

This sequence does not affect any other I2C devices

which may be on the bus, as they should disregard this

as an invalid command.

8.10

Design Considerations

In the design of a system with the MCP47FVBXX

devices, the following considerations should be taken

into account:

• Power Supply Considerations

• Layout Considerations

8.10.1

POWER SUPPLY

CONSIDERATIONS

The typical application will require a bypass capacitor

in order to filter high-frequency noise, which can be

induced onto the power supply's traces. The bypass

capacitor helps to minimize the effect of these noise

sources on signal integrity. Figure 8-10 illustrates an

appropriate bypass strategy.

In this example, the recommended bypass capacitor

value is 0.1 µF. This capacitor should be placed as close

(within 4 mm) to the device power pin (VDD) as possible.

The power source supplying these devices should be

as clean as possible. If the application circuit has

separate digital and analog power supplies, VDD and

VSS should reside on the analog plane.

FIGURE 8-10:

Typical Microcontroller

Connections.

Note:

This technique is documented in AN1028.

Note:

The potential for this erroneous write

ONLY occurs if the master device is reset

while sending a Write command to the

MCP47FVBxx.

S‘1’‘1’‘1’‘1’‘1’‘1’‘1’‘1’

Start bit

Nine bits of ‘1’

Start bit

Stop bit

VDD

VSS

0.1 µF

SCL

VOUT

VREF

SDA

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