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ZLP12840 数据表(PDF) 22 Page - Zilog, Inc. |
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ZLP12840 数据表(HTML) 22 Page - Zilog, Inc. |
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22 / 58 page ![]() PS024406-0106 P R E L I M I N A R Y I/O Port Pin Functions ZLP12840 OTP MCU Product Specification 11 I/O Port Pin Functions The ZLP12840 MCU features three 8-bit ports, which are described below. Port 0 is nibble-programmable as either input or output Port 2 is bit-programmable as either input or output Port 3 features four inputs on the lower nibble and four outputs on the upper nibble Port 0 and 2 internal pull-ups are disabled on any pin or group of pins when programmed into output mode. The CMOS input buffer for each port 0 or 2 pin is always connected to the pin, even when the pin is configured as an output. If the pin is configured as an open-drain output and no external signal is applied, a High output state can cause the CMOS input buffer to float. This might lead to excessive leakage current of more than 100 A. To prevent this leakage, connect the pin to an external signal with a defined logic level or ensure its output state is Low, especially during STOP mode. Port 0, 1, and 2 have both input and output capability. The input logic is always present no matter whether the port is configured as input or output. When doing a READ in- struction, the MCU reads the actual value at the input logic but not from the output buff- er. In addition, the instructions of OR, AND, and XOR have the Read-Modify-Write sequence. The MCU first reads the port, and then modifies the value and load back to the port. Precaution must be taken if the port is configured as open-drain output or if the port is driving any circuit that makes the voltage different from the desired output logic. For example, pins P00P07 are not connected to anything else. If it is configured as open- drain output with output logic as ONE, it is a floating port and reads back as ZERO. The following instruction sets P00-P07 all LOW. ßÒÜ ÐðôýûÚð Table 7 summarizes the registers used to control I/O ports. Some port pin functions can also be affected by control registers for other peripheral functions. Table 7. I/O Port Control Registers Address (Hex) Reset 12-Bit Bank 8-Bit Register Description Mnemonic Page # 00003 00 Port 0 P0 XXh 22 00203 02 Port 2 P2 XXh 24 Note: Caution: |
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