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ZLP12840 数据表(PDF) 54 Page - Zilog, Inc. |
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ZLP12840 数据表(HTML) 54 Page - Zilog, Inc. |
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54 / 58 page ![]() PS024406-0106 P R E L I M I N A R Y UART ZLP12840 OTP MCU Product Specification 43 UART The universal asynchronous receiver/transmitter (UART) is a full-duplex communication channel capable of handling asynchronous data transfers. The two UARTs use a single 8-bit data mode with selectable parity. Features of the UARTs include: 8-bit asynchronous data transfer Selectable even- and odd-parity generation and checking One or two Stop bits Separate transmit and receive interrupts Framing, overrun, and break detection Separate transmit and receive enables 8-bit Baud Rate Generator (BRG) Baud Rate Generator timer mode UART operational during HALT mode Architecture The UARTs consist of three primary functional blocks: transmitter, receiver, and Baud Rate Generator. The UART transmitter and receiver function independently, but employ the same baud rate and data format. Figure 13 illustrates the UART architecture. Table 21. UART Control Registers Address (Hex) Reset 12-Bit Bank 8-Bit Register Description Mnemonic Page # 0F1 All F1 UART Receive/Transmit Data Register URDATA/ UTDATA XXh 52 0F2 All F2 UART Status Register UST 0000_0010b 53 0F3 All F3 UART Control Register UCTL 00h 54 0F4 All F4 UART Baud Rate Generator Constant BCNST FFh 55 |
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