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ZLP12840 数据表(PDF) 36 Page - Zilog, Inc. |
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ZLP12840 数据表(HTML) 36 Page - Zilog, Inc. |
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36 / 58 page ![]() PS024406-0106 P R E L I M I N A R Y Port 3 Mode Register ZLP12840 OTP MCU Product Specification 25 Port 3 Mode Register The Port 3 Mode Register is used primarily to configure the functionality of the Port 3 inputs. When bit 2 is set, the IR Learning Amplifier is used instead of the COMP1 com- parator, regardless of the value of bit 1. See Table 14. This register is not reset after a stop-mode recovery. Table 14. Port 3 Mode Register (P3M) Bit 7 6 5 4 3 2 1 0 Field Reserved IR Learning Amplifier Digital/Analog Mode Port 2 Open- Drain Reset X X X X X 0 0 0 R/W W WW Address Bank Independent: F7h; Linear 0F7h Bit Position R/W Value Description [7:3] ReservedWrites have no effect. Reads return 11111b. [2] W0 1 IR Learning Amplifier disabled. IR Learning Amplifier enabled with P31 configured as amplifier input. [1] W 0 1 Digital/Analog Mode P30, P31, P32, P33 are digital inputs. P30, P32, and P33 are comparator inputs. If P3M[2]=0, P31 is also a comparator input. If P3M[2]=1, P31 is the IR amplifier input. [0] W0 1 Port 2 open-drain. Port 2 push/pull. Note: |
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