ZLP12840 datasheet(50/58 Pages) ZILOG

50 / 58 page

PS024406-0106

P R E L I M I N A R Y

ZLP12840 OTP MCU

Product Specification

Table 20 maps each linear (12-bit) register file address to the associated register, mne-

monic, and reset value. The table also lists the register bank (or banks) and corresponding

8-bit address, if any, for each register, plus a page link to the detailed register diagram.

Throughout this book, an X in a number denotes an undefined digit. A (dash) in a

table cell indicates that the corresponding attribute does not apply to the listed item. Reset

value digits highlighted in grey are not reset by a stop-mode recovery. Register bit

SMR[7] (shown in boldface) is set to 1 instead of reset by a stop-mode recovery.

Table 20. Register File Address Summary

Address (Hex)

Reset

12-Bit

Bank 8-Bit

Mnemonic

Page #

00003

Port 0

XXh

00103

Reserved

00203

Port 2

XXh

00303

Port 3

0Xh

00400F 0

040F General-Purpose Registers (Bank 0 Only)

XXh

0100EF 0,D,F 10EF General-Purpose Registers (Banks 0, D, F)

XXh

0F0

All

Program Memory Paging Register

PMPR

0 XXX_XXX0b

0F1

All

UART Receive/Transmit Data Register

URDATA/

UTDATA

XXh

0F2

All

UART Status Register

UST

0 0 00 _00 1 0b

0F3

All

UART Control Register

UCTL

00h

0F4

All

UART Baud Rate Generator Constant

BCNST

FFh

0F5

All

Reserved

0F6

All

Port 2 Mode Register

P2M

FFh

0F7

All

Port 3 Mode Register

P3M

XXXX_X0 0 0b

0F8

All

Port 0 Mode Register

P01M

X1 XX_XXX1b

0F9

All

Interrupt Priority Register

IPR

XXh

0FA

All

Interrupt Request Register

IRQ

00h

0FB

All

Interrupt Mask Register

IMR

0 XXX_XXXXb

0FC

All

Flags Register

FLAGS

XXh

115

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