ZLP12840 datasheet(34/58 Pages) ZILOG

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PS024406-0106

P R E L I M I N A R Y

Port 2 Mode Register

ZLP12840 OTP MCU

Product Specification

Port 2 Mode Register

The Port 2 Mode Register determines the I/O direction of each bit on Port 2. Bit 0 of the

Port 3 Mode Register determines whether the output drive is push/pull or open-drain. See

Table 12.

This register is not reset after a stop-mode recovery.

Table 12. Port 2 Mode Register (P2M)

Bit

Field

P27 I/O

Definition

P26 I/O

Definition

P25 I/O

Definition

P24 I/O

Definition

P23 I/O

Definition

P22 I/O

Definition

P21 I/O

Definition

P20 I/O

Definition

Reset

R/W

Address

Bank Independent: F6h; Linear: 0F6h

Bit

Position

Value Description

[7]0

Defines P27 as output.

Defines P27 as input.

[6]0

Defines P26 as output.

Defines P26 as input.

[5]0

Defines P25 as output.

Defines P25 as input.

[4]0

Defines P24 as output.

Defines P24 as input.

[3]0

Defines P23 as output.

Defines P23 as input.

[2]0

Defines P22 as output.

Defines P22 as input.

[1]0

Defines P21 as output.

Defines P21 as input.

[0]0

Defines P20 as output.

Defines P20 as input.

Note:

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