ZLP12840 datasheet(57/58 Pages) ZILOG

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PS024406-0106

P R E L I M I N A R Y

Operation

ZLP12840 OTP MCU

Product Specification

7. Before disabling the transmitter, read the transmit completion status bit, UST[1]. If

UST[1]=0, continue to monitor the bit until it changes to 1, which indicates that all

data in the Transmit Data and internal shift registers has been transmitted.

Data written while the transmit enable bit is clear (UCTL[7]=0) will not be transmitted.

Data written while the transmit data status bit is clear (UST[2]=0) overwrites the previ-

ous value written, so the previous written value will not be transmitted. Disabling the

UART transmitter while the transmit completion status bit is clear (UST[1]=0) can cor-

rupt the byte being transmitted.

Transmitting Data Using the Interrupt-Driven Method

The UART transmitter interrupt indicates the availability of the Transmit Data register to

accept new data for transmission. Follow these steps to configure the UART for interrupt-

driven data transmission:

1. Write to the BCNST register to set the appropriate baud rate.

2. Write a 0 to bit 6 of the P01M register.

3. Execute a DI instruction to disable interrupts.

4. Write to the Interrupt control registers to enable the UART Transmitter interrupt and

set the appropriate priority.

5. Write to the UART Control register to:

a. Set the transmit enable bit (UCTL bit 7) to enable the UART for data transmission.

b. Enable parity, if appropriate, and select either even or odd parity.

6. Execute an EI instruction to enable interrupts.

7. Because the transmit buffer is empty, an interrupt is immediately executed.

8. Write the data byte to the UART Transmit Data register. The transmitter automatically

transfers the data to the internal transmit shift register and transmits the data.

9. Execute the IRET instruction to return from the interrupt-service routine and wait for

the Transmit Data register to again become empty.

10. Before disabling the transmitter, read the transmit completion status bit, UST[1]. If

UST[1]=0, continue to monitor the bit until it changes to 1, which indicates that all

data in the Transmit Data and internal shift registers has been transmitted.

Data written while the transmit enable bit is clear (UCTL[7]=0) will not be transmitted.

Data written while the transmit data status bit is clear (UST[2]=0) overwrites the previ-

ous value written, so the previous written value will not be transmitted. Disabling the

UART transmitter while the transmit completion status bit is clear (UST[1]=0) can cor-

rupt the byte being transmitted.

Caution:

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