ADIN1110CCPZ-R7 datasheet(31/104 Pages) AD

31 / 104 page

Data Sheet

ADIN1110

MAC SPI

analog.com

Rev. 0 | 31 of 104

Table 26. Frame Header

D15 to D11

D10

D9 to D8

D7 to D6

D5 to D4

D1 to D0

Reserved

Priority

Reserved

EGRESS_CAPTURE

Reserved

TIME_STAMP_PARITY

TIME_STAMP_PRESENT

Reserved

See the following definitions:

►

Priority: indicates which priority queue the frame was received

from. Not used on transmit. Set 0 in transmitted frames.

►

EGRESS_CAPTURE: capture an egress time stamp into the

host readable egress time registers, as follows:

►

00: no action.

►

01: capture in the pair of TTSCAL and TTSCAH registers. The

TTSCAA bits in the STATUS0 register assert when captured.

►

10: capture in the pair of TTSCBL and TTSCBH registers. The

TTSCAB bits in the STATUS0 register assert when captured.

►

11: capture in the pair of TTSCCL and TTSCCH registers. The

TTSCAC bits in the STATUS0 register assert when captured.

►

TIME_STAMP_PARITY: odd parity for the appended time stamp.

Not used on transmit. Set to 0 in transmitted frames.

►

TIME_STAMP_PRESENT: on receive, the first 4 bytes or 8 bytes

of data contain the time stamp for the frame. Not used on

transmit. Set to 0 in transmitted frames.

►

Reserved: always set to 0.

Receive Frame over SPI

The following procedure must be followed to receive an Ethernet

frame when using the generic SPI protocol in store and forward

mode:

1. The device defaults to operating in store and forward mode.

2. Set the P1_RX_RDY_MASK bit to 0 to enable an interrupt

when a full frame is received.

3. If the P1_RX_RDY bit is asserted, read the MAC receive frame

size register to determine the size of the received frame.

4. Read the frame via the MAC receive register. It is possible to

burst read the entire frame or split it up into multiple smaller

burst reads. The first byte of the received frame is returned

in P1_RX, Bits[31:24]. The burst read transaction must be a

multiple of 4 bytes. Some of the last 4 bytes are padded with 0s

if the frame is not a multiple of 4 bytes in size.

5. Read P1_RX_RDY again. If the value of the bit is 1, another

frame is available to read. Repeat from Step 3.

Cut Through

The generic SPI protocol supports cut through mode for transmit

operations.

Before transmitting any frames, write 1 to the transmit cut through

enable bits.

The threshold at which the frame transmit starts can be modified via

the host transmit start threshold (see the Transmit Threshold Regis-

ter section). This register has a default value of 1. Therefore, by

default, transmit starts immediately on writing to the host transmit

FIFO.

To ensure that the frame transmission does not under run, the host

transmit FIFO has to be written at a rate greater than 10 Mbps. If

the frame under runs, the host transmit under run error bit asserts.

Generic SPI Errors

Generic SPI CRC Error

If an SPI CRC error occurs on a write to a register, the register is

not written.

If the write is to the transmit register, the transmit FIFO is missing

data and must be cleared by the host. Similarly, a read of the

receive register has missing data in the receive frame, and the

FIFO must be cleared.

If the errored transaction was a write to a configuration register,

the SPI host must issue the write again. If the software does not

know which configuration, the MAC must be reset by writing the

RST_MAC_ONLY keys to the SOFT_RST register.

Generic SPI Transmit Protocol Error (TXPE)

TXPE asserts when the TX_FSIZE register is written, but the MAC

still expects further writes to the transmit register related to the

previous frame size written to the TX_FSIZE register. This error

does not occur in normal operation and indicates an issue with

the software driver, for example, two consecutive writes to the

TX_FSIZE register without any writes to the transmit register.

In response to the assertion of TXPE, the host must clear the

transmit FIFO.

OPEN ALLIANCE SPI PROTOCOL

The OPEN Alliance SPI protocol Version 1.0 can transfer data over

the SPI using full duplex operation, achieving 10 Mbps bidirectional

frame transfer with an SPI clock frequency in the region of 12 MHz

to 16 MHz or greater.

The ADIN1110 supports the following OPEN Alliance SPI capabil-

ities (see the Supported Capabilities Register section for more

details):

►

Transmit FCS validation

►

Cut through

►

IEEE 1588 time stamp capture on transmit and receive

►

Minimum supported chunk size is 8 bytes

ADIN1110CCPZ-R7 数据表(PDF) 31 Page - Analog Devices

ADIN1110CCPZ-R7 数据表(HTML) 31 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

ADIN1110CCPZ-R7 数据表(PDF) 31 Page - Analog Devices

ADIN1110CCPZ-R7 数据表(HTML) 31 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载