ADIN1110CCPZ-R7 datasheet(6/104 Pages) AD

6 / 104 page

Data Sheet

ADIN1110

TIMING CHARACTERISTICS

analog.com

Rev. 0 | 6 of 104

POWER-UP TIMING

Table 3. Power-Up Timing

Parameter

Description

Min

Typ

Max

Unit

tRAMP

Power supply ramp time

Minimum time interval to internal power good1

Hardware configuration latch time

μs

Management interface (SPI) active

1 The minimum time interval is referenced to the last supply to reach its rising threshold. There is no specific power supply sequencing required.

Figure 2. Power-Up Timing

SPI

Table 4.

Parameter1, 2

Description

Min

Typ

Max

Unit

SCLK cycle time

SCLK high time

SCLK low time

CS falling edge to SCLK rising edge setup time

Last SCLK rising edge to CS rising edge

CS high time

Data setup time

Data hold time

t9 3

SCLK falling edge to SDO valid

t10 3

CS rising edge to SDO tristate

t11 3

CS falling edge to SDO valid (for readback MSB only)

1 Guaranteed by design and characterization. Not production tested.

2 All input signals are specified with rise time (tR) = fall time (tF) = 5 ns (10% to 90% of VDDIO) and timed from a voltage level of 1.2 V.

3 Capacitive load on the SDO pin is 10 pF.

ADIN1110CCPZ-R7 数据表(PDF) 6 Page - Analog Devices

ADIN1110CCPZ-R7 数据表(HTML) 6 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载