ADIN1110CCPZ-R7 datasheet(38/104 Pages) AD

38 / 104 page

Data Sheet

ADIN1110

MAC SPI

analog.com

Rev. 0 | 38 of 104

►

Transmit Buffer Overflow. Occurs when attempting to write trans-

mit frame data to the MAC-PHY when there is no transmit buffer

space available as indicated by the transmit credit field (TXC) of

the previous data footer. In this condition, the MAC-PHY ignores

the transmit data chunk and sets the host transmit FIFO overflow

bit, and the frame data already in the buffer is dropped.

►

Transmit Buffer Under Run. This error can only occur in cut

through mode. The SPI host must always send frame data to

the MAC-PHY faster than the network to avoid this error. When

this error occurs, the host transmit FIFO under run error bit is

set, and the MAC-PHY terminates the frame being transmitted

in a way that invalidates the frame. Additionally, the MAC-PHY

ignores any additional frame data received from the SPI host

until it receives an end of frame indication (EV = 1).

►

Loss of Framing Error. This error occurs when the CS signal is

deasserted before the expected end of the data chunk or control

command. The MAC-PHY and the loss of frame error is set, any

transmit frame in progress is dropped, and any receive frame in

progress of being sent to the SPI host is terminated.

►

Receive Buffer Overflow. This error occurs when the SPI host

does not read frame data from the MAC-PHY fast enough. This

error can occur both in store and forward and cut through modes.

When this error occurs, the MAC-PHY terminates the frame

being received from the PHY. In store and forward mode, no

portion of the frame is transferred to the SPI host. In cut through

mode, the MAC-PHY terminates the frame (EV = 1) with frame

drop set (FD = 1).

►

Control Data Protection Error. The control data protection error

(CDPE) and the loss of frame error (LOFE) bits assert when

protection is enabled on the OPEN Alliance SPI and there is an

error on write data received from the host. The write does not

complete in this case.

If possible, the software executes the write again. If software

does not know which configuration register was written, the de-

vice might not be configured properly. In this case, the MAC must

be reset by writing the RST_MAC_ONLY keys to the software

reset register.

FRAME FILTERING ON RECEIVE

By default, the device filters all frames received. To receive frames,

set up the address filtering table, or the default operation for all

received frames can be changed.

The device can be configured to filter up to 16 different MAC

addresses based on the destination MAC address (DA).

To receive frames with a particular DA, that DA has to be program-

med to one of the 16 ADDR_FILT_x registers. Each register is 32

bits wide. Therefore, for example, to program a DA of 0800 005A

646B to ADDR_FILT[0], write the following:

1. 0x0800 to ADDR_FILT_UPR0.

2. 0x005A6468 to ADDR_FILT_LWR0.

To forward frames with this DA to the host, set the TO_HOST

bit within the ADDR_FILT_UPRn to 1. To apply this rule, set the

APPLY2PORT1 bit to 1.

MAC addresses can be masked using the ADDR_MSK_x registers.

For example, to receive all the MAC addresses in the range 0x8000

005A 64xx, write:

1. 0xFFFF to ADDR_MSK_UPR0.

2. 0XFFFFFF00 to ADDR_MSK_LWR0.

Frames that do not match any of the 16 ADDR_FILT_x registers

are dropped by default. If the P1_FWD_UNK2HOST bits within the

HOST_CFG register are set to 1, all frames that do not match a DA

are forwarded to the host. Figure 29 shows the filtering algorithm.

Figure 29. Filtering Algorithm

Frames received with a bad CRC or with RX_ER asserted from the

PHY, as well as runt and jabber frames, are dropped and counted.

Receive Priority Queues

There are two different FIFOs on receive: a high priority FIFO and a

low priority FIFO.

By default, the low priority FIFO is configured to 12 kB, and the

high priority FIFO is configured to 8 kB. The sizes of these FIFOs

can be changed before receiving or transmitting any frames via

the P1_RX_LO_SIZE and P1_RX_HI_SIZE fields in the FIFO_SIZE

Frames are always returned from the high priority FIFO first.

ADIN1110CCPZ-R7 数据表(PDF) 38 Page - Analog Devices

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