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ADIN1110CCPZ-R7 数据表(PDF) 42 Page - Analog Devices |
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ADIN1110CCPZ-R7 数据表(HTML) 42 Page - Analog Devices |
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42 / 104 page  Data Sheet ADIN1110 REGISTERS analog.com Rev. 0 | 42 of 104 SPI REGISTER MAP Table 34. SPI Register Map Address Name Description Reset Access 0x00 IDVER Identification Version Register. 0x00000010 R 0x01 PHYID PHY Identification Register. 0x0283BC91 R 0x02 CAPABILITY Supported Capabilities Register. 0x000006C3 R 0x03 RESET Reset Control and Status Register. 0x00000000 W 0x04 CONFIG0 Configuration Register 0. 0x00000006 R/W 0x06 CONFIG2 Configuration Register 2. 0x00000800 R/W 0x08 STATUS0 Status Register 0. 0x00000040 R/W 0x09 STATUS1 Status Register 1. 0x00000000 R/W 0x0B BUFSTS Buffer Status Register. 0x00007700 R 0x0C IMASK0 Interrupt Mask Register 0. 0x00001FBF R/W 0x0D IMASK1 Mask Bits for Driving the Interrupt Pin Register. 0x43FA1F1A R/W 0x10 TTSCAH Transmit Time Stamp Capture Register A (High). 0x00000000 R 0x11 TTSCAL Transmit Time Stamp Capture Register A (Low). 0x00000000 R 0x12 TTSCBH Transmit Time Stamp Capture Register B (High). 0x00000000 R 0x13 TTSCBL Transmit Time Stamp Capture Register B (Low). 0x00000000 R 0x14 TTSCCH Transmit Time Stamp Capture Register C (High). 0x00000000 R 0x15 TTSCCL Transmit Time Stamp Capture Register C (Low). 0x00000000 R 0x20 to 0x27 by 1 MDIOACCn MDIO Access Registers. 0x8C000000 R/W 0x30 TX_FSIZE MAC Tx Frame Size Register. 0x00000000 R/W 0x31 TX MAC Transmit Register. 0x00000000 W 0x32 TX_SPACE Tx FIFO Space Register. 0x00000FFF R 0x34 TX_THRESH Transmit Threshold Register. 0x00000041 R/W 0x36 FIFO_CLR MAC FIFO Clear Register. 0x00000000 W 0x37 to 0x3A by 1 SCRATCHn Scratch Registers. 0x00000000 R/W 0x3B MAC_RST_STATUS MAC Reset Status. 0x00000003 R 0x3C SOFT_RST Software Reset Register. 0x00000000 W 0x3D SPI_INJ_ERR Inject an Error on MISO from the DUT. 0x00000000 R/W 0x3E FIFO_SIZE FIFO Sizes Register. 0x00000464 R/W 0x3F TFC Tx FIFO Frame Count Register. 0x00000000 R 0x40 TXSIZE Tx FIFO Valid Half Words Register. 0x00000000 R 0x41 HTX_OVF_FRM_CNT Host Tx Frames Dropped Due to FIFO Overflow. 0x00000000 R 0x42 MECC_ERR_ADDR Address of a Detected ECC Error in Memory. 0x00000000 R 0x43 to 0x49 by 1 CECC_ERRn Corrected ECC Error Counters. 0x00000000 R 0x50 to 0x6E by 2 ADDR_FILT_UPRn MAC Address Rule and DA Filter Upper 16 Bits Registers. 0x00000000 R/W 0x51 to 0x6F by 2 ADDR_FILT_LWRn MAC Address DA Filter Lower 32 Bits Registers. 0x00000000 R/W 0x70 to 0x72 by 2 ADDR_MSK_UPRn Upper 16 Bits of the MAC Address Mask. 0x0000FFFF R/W 0x71 to 0x73 by 2 ADDR_MSK_LWRn Lower 32 Bits of the MAC Address Mask. 0xFFFFFFFF R/W 0x80 TS_ADDEND Time Stamp Accumulator Addend Register. 0x85555555 R/W 0x81 TS_1SEC_CMP Timer Update Compare Register. 0x3B9ACA00 R/W 0x82 TS_SEC_CNT Seconds Counter Register. 0x00000000 R/W 0x83 TS_NS_CNT Nanoseconds Counter Register. 0x00000000 R/W 0x84 TS_CFG Timer Configuration Register. 0x00000000 R/W 0x85 TS_TIMER_HI High Period for TS_TIMER Register. 0x00000000 R/W 0x86 TS_TIMER_LO Low Period for TS_TIMER Register. 0x00000000 R/W 0x87 TS_TIMER_QE_CORR Quantization Error Correction Register. 0x00000000 R/W |
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