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ADIN1110CCPZ-R7 数据表(PDF) 98 Page - Analog Devices |
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ADIN1110CCPZ-R7 数据表(HTML) 98 Page - Analog Devices |
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98 / 104 page  Data Sheet ADIN1110 REGISTERS analog.com Rev. 0 | 98 of 104 This register is a latched copy of the frame length error counter register. This register is a count of received frames with a length error status. When the receive error counter (RX_ERR_CNT) is read, the frame length error counter register is latched, which ensures that the frame length error count and receive frame count are synchronized. Table 198. Bit Descriptions for FC_LEN_ERR_CNT Bits Bit Name Description Reset Access [15:0] FC_LEN_ERR_CNT Latched Copy of the Frame Length Error Counter. 0x0 R Frame Checker Alignment Error Count Register Device Address: 0x1F; Register Address: 0x800C, Reset: 0x0000, Name: FC_ALGN_ERR_CNT This register is a latched copy of the frame alignment error counter register. This register is a count of received frames with an alignment error status. When the receive error counter (RX_ERR_CNT) is read, the alignment error counter is latched, which ensures that the frame alignment error count and the receive frame count are synchronized. Table 199. Bit Descriptions for FC_ALGN_ERR_CNT Bits Bit Name Description Reset Access [15:0] FC_ALGN_ERR_CNT Latched Copy of the Frame Alignment Error Counter. 0x0 R Frame Checker Symbol Error Count Register Device Address: 0x1F; Register Address: 0x800D, Reset: 0x0000, Name: FC_SYMB_ERR_CNT This register is a latched copy of the symbol error counter register. This register is a count of received frames with both RX_ER and RX_DV set. When the receive error counter (RX_ERR_CNT) is read, the symbol error count is latched, which ensures that the symbol error count and the frame receive count are synchronized. Table 200. Bit Descriptions for FC_SYMB_ERR_CNT Bits Bit Name Description Reset Access [15:0] FC_SYMB_ERR_CNT Latched Copy of the Symbol Error Counter. 0x0 R Frame Checker Oversized Frame Count Register Device Address: 0x1F; Register Address: 0x800E, Reset: 0x0000, Name: FC_OSZ_CNT This register is a latched copy of the oversized frame error counter register. This register is a count of receiver frames with a length greater than specified in frame checker maximum frame size (FC_MAX_FRM_SIZE). When the receive error counter (RX_ERR_CNT) is read, the oversized frame counter register is latched, which ensures that the oversized error count and the receive frame count are synchronized. Table 201. Bit Descriptions for FC_OSZ_CNT Bits Bit Name Description Reset Access [15:0] FC_OSZ_CNT Latched copy of the Oversized Frame Error Counter. 0x0 R Frame Checker Undersized Frame Count Register Device Address: 0x1F; Register Address: 0x800F, Reset: 0x0000, Name: FC_USZ_CNT This register is a latched copy of the undersized frame error counter register. This register is a count of received frames with less than 64 bytes. When the receive error counter (RX_ERR_CNT) is read, the undersized frame error counter is latched, which ensures that the undersized frame error count and the receive frame count are synchronized. |
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