ADIN1110CCPZ-R7 datasheet(14/104 Pages) AD

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Data Sheet

ADIN1110

THEORY OF OPERATION

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Rev. 0 | 14 of 104

held in tristate mode, the hardware configuration pins are latched,

and the I/O pins are configured for their functional mode. The crys-

tal oscillator circuit is enabled, and after the crystal starts up and

stabilizes, the PLL is enabled. Approximately 10 ms (maximum)

after writing the SOFT_RST keys, the internal logic is released from

reset and all the management interface registers are accessible.

MAC Subsystem Reset

A MAC only software reset is initiated by writing the required pair of

keys to the SOFT_RST register.

The reset is applied for about 1.2 µs. The MAC subsystem reset

interrupts any transmit/receive packet exchange between the MAC

and the PHY, but does not drop any existing link nor prevents

a link from establishing. The PHY management registers are not

initialized.

The PHY needs to be out of software power-down to trigger a MAC

only software reset.

PHY Subsystem Reset

The PHY subsystem is the part of the ADIN1110 that incorporates

the 10BASE-T1L PHY transceiver analog and digital circuits. A

PHY subsystem reset is initiated by setting the PHY subsystem

reset register bit (CRSM_PHY_SUBSYS_RST). When this bit is

set, the PHY subsystem is reset. The reset is applied for about

1.2 µs and then this bit self clears. All of the PHY digital circuitry

is reset and any existing link drops. The management registers

are not initialized by this reset, and access to all the management

registers is available during the PHY subsystem reset. This is a

short reset and can be used to put the device into a known state

while retaining any software initialization of the device.

LED FUNCTIONS

LED_0 and LED_1 can be configured to display various activities

of the ADIN1110 using the LED function feature. The LED function

is configurable using the LED0_FUNCTION and LED1_FUNCTION

bits (see the LED Control Register section).

The 7, 8, 9, and 10 (decimal) bit settings for LEDx_FUNCTION are

not available in LED Mode 2.

Table 9. LED_x Pins Configuration Summary

Parameter

LED_0

LED_1

Pin Number

Internal Pull-Up or Pull-

Down Resistor

Pull-up

Pull-down

Status at Power-Up or

Reset

Enabled

Disabled

LED Pin Mux

Not applicable

DIGIO_LED1_PINMUX bits (see the Pin Mux Configuration 1 Register

section)

Enable LED

LED0_EN bit (see the LED Control Register section)

LED1_EN bit (see the LED Control Register section)

LED Polarity

LED0_POLARITY bits (see the LED Polarity Register section)

LED1_POLARITY bits (see the LED Polarity Register section)

LED Mode

LED0_MODE bit (see the LED Control Register section), default: LED

Mode 1

LED1_MODE bit (see the LED Control Register section), default: LED

Mode 1

LED Function1

LED0_FUNCTION bits (see the LED Control Register section), default:

LINKUP_TXRX_ACTIVITY

LED1_FUNCTION bits (see the LED Control Register section), default:

TXRX_ACTIVITY

LED Blink Rate

LED0_BLINK_TIME_CNTRL (see the LED_0 On/Off Blink Time Register

section)

LED1_BLINK_TIME_CNTRL (see the LED 1 On/Off Blink Time Register

section

Maximum Current2

8 mA at 3.3 V

1 The 7, 8, 9, and 10 (decimal) settings in the LEDx_FUNCTION bits are not available in LED Mode 2.

2 See Table 2.

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