ADIN1110CCPZ-R7 datasheet(13/104 Pages) AD

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Data Sheet

ADIN1110

THEORY OF OPERATION

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Rev. 0 | 13 of 104

V, and at least one PHY must request 2.4 V p-p transmit level

operation.

If it is required to only operate the PHY at 1.0 V p-p transmit

level operation, AN_ADV_B10L_TX_LVL_HI_ABL must be 0 so

that 2.4 V p-p transmit level operation is not advertised. In this

case, autonegotiation can only resolve to 1.0 V p-p transmit level

operation, irrespective of what setting the remote PHY advertises.

Master/Slave Resolution

Autonegotiation is also used to resolve master or slave status. The

PHY can be configured to prefer slave or prefer master through

the hardware configuration (see Table 12). If autonegotiation is

disabled, the MS_SEL hardware configuration pin sets the default

master/slave selection. Note that the recommended use of the

ADIN1110 is with autonegotiation enabled.

During autonegotiation, when prefer slave is selected, and the

remote end is prefer or forced master, the local PHY is set to slave

(and remote to master). When the remote end is prefer or forced

slave, the local PHY is set to master (and remote to slave).

MDI INTERFACE

The media dependent interface (MDI) connects the ADIN1110 to

the Ethernet network via a twisted wire pair.

The ADIN1110 requires an external hybrid between the TXN/TXP

and RXN/RXP pins and the twisted wire pair. This external hybrid

allows the system to have full duplex communication by removing

the local transmit signal from the combined signal on the cable,

leaving the desired receive signal.

The ADIN1110 hybrid requires a specific topology and values for

proper operation. Figure 10 shows the topology and values for

the components. Consider the size, power, and voltage rating of

these components in the context of other system requirements, for

example, requirements of intrinsic safety.

Figure 10. Recommended Hybrid for the ADIN1110

RESET OPERATION

The ADIN1110 supports the following chip resets:

►

Power-on reset

►

Hardware reset

►

Software reset

►

MAC subsystem reset

►

PHY subsystem reset

All of these resets put the ADIN1110, including the PHY core and

MAC, into a known state. Whenever the MAC is reset, the SDO pin

is pulled down and the TS_TIMER pin is driven to a low state.

Power-On Reset

The ADIN1110 includes power monitoring circuitry to monitor all of

the supplies. During power-up, the ADIN1110 is held in hardware

reset until each of the supplies has crossed its minimum rising

threshold value and the power is considered good.

The POR module includes brownout protection by monitoring the

supplies to detect if one or more of the supplies falls below a

minimum falling threshold value. If brownout detection occurs, the

device is held in hardware reset until the power is good.

Hardware Reset

A hardware reset is initiated by the power-on reset circuitry or

by asserting the RESET pin low. Bring the RESET pin low for a

minimum of 10 µs. Deglitch circuitry is included on this pin to reject

pulses shorter than 0.3 μs.

When the RESET pin is deasserted, all the input/output (I/O) pins

are held in tristate mode, the hardware configuration pins are latch-

ed, and the I/O pins are configured for their functional mode. When

all the external and internal supplies are valid and stable, the crystal

oscillator circuit is enabled. After the crystal starts up and stabilizes,

the phase-locked loop PLL is enabled. After approximately 50 ms

(maximum) from the deassertion of the RESET pin, all the internal

clocks are valid, internal logic is released from reset, and all the

management interface registers are accessible so that the device

can be programmed.

Software Reset

A full chip software reset can be initiated by writing 1 to the

SWRESET field of the RESET register.

If a transmission is taking place when the SPI software reset is initi-

ated, the frame transmission stops abruptly and a runt or a frame

with a bad cyclic redundancy check (CRC) may be transmitted.

Once the MAC-PHY is reset, the ADIN1110 is ready to bring up

links.

When this software reset is initiated, a full initialization of the chip,

almost equivalent to a hardware reset, is done. The I/O pins are

ADIN1110CCPZ-R7 数据表(PDF) 13 Page - Analog Devices

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