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ADIN1110CCPZ-R7 数据表(PDF) 100 Page - Analog Devices |
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ADIN1110CCPZ-R7 数据表(HTML) 100 Page - Analog Devices |
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100 / 104 page  Data Sheet ADIN1110 REGISTERS analog.com Rev. 0 | 100 of 104 Frame Generator Control/Restart Register Device Address: 0x1F; Register Address: 0x8021, Reset: 0x0001, Name: FG_CNTRL_RSTRT This register controls the frame generator. The FG_CNTRL bit field specifies data field type used by the frame generator, for example, random all zeros. The FG_RSTRT bit restarts the frame generator. Table 207. Bit Descriptions for FG_CNTRL_RSTRT Bits Bit Name Description Reset Access [15:4] RESERVED Reserved. 0x0 R 3 FG_RSTRT Frame Generator Restart. When set, this bit restarts the frame generator. This bit is self clearing 0x0 R/W SC [2:0] FG_CNTRL Frame Generator Control. 0x1 R/W 000: no frames after completion of current frame. 001: random number data frame. 010: all zeros data frame. 011: all ones data frame. 100: alternative 0x55 data field. 101: data field decrementing from 255 (decimal) to 0. Frame Generator Continuous Mode Enable Register Device Address: 0x1F; Register Address: 0x8022, Reset: 0x0000, Name: FG_CONT_MODE_EN This register is used to put the frame generator into continuous mode. The default mode of operation is burst mode, where the number of frames generated is specified by the FG_NFRM_H and FG_NFRM_L registers. Table 208. Bit Descriptions for FG_CONT_MODE_EN Bits Bit Name Description Reset Access [15:1] RESERVED Reserved. 0x0 R 0 FG_CONT_MODE_EN Frame Generator Continuous Mode Enable. This bit is used to put the frame generator into continuous mode or burst mode. 0x0 R/W 1: frame generator operates in continuous mode. In this mode, the frame generator keeps generating frames indefinitely. 0: frame generator operates in burst mode. In this mode, the frame generator generates a single burst of frames and then stops. The number of frames is determined by the FG_NFRM_H and FG_NFRM_L registers. Frame Generator Interrupt Enable Register Device Address: 0x1F; Register Address: 0x8023, Reset: 0x0000, Name: FG_IRQ_EN This register is used to enable the frame generator interrupt. An interrupt is generated when the requested number of frames is generated. Enable the frame checker/generator interrupt in the PHY_SUBSYS_IRQ_MASK register. Set the MAC_IF_FC_FG_IRQ_EN bit. The interrupt status can be read via the MAC_IF_FC_FG_IRQ_LH bit in the PHY_SUBSYS_IRQ_STATUS register. Table 209. Bit Descriptions for FG_IRQ_EN Bits Bit Name Description Reset Access [15:1] RESERVED Reserved. 0x0 R 0 FG_IRQ_EN Frame Generator Interrupt Enable. When set, this bit indicates that the frame generator must generate an interrupt when it has transmitted the programmed number of frames. 0x0 R/W 1: enable the frame generator interrupt. 0: disable the frame generator interrupt. |
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