ADIN1110CCPZ-R7 datasheet(103/104 Pages) AD

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Data Sheet

ADIN1110

PCB LAYOUT RECOMMENDATIONS

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Rev. 0 | 103 of 104

This section details the key areas of interest for the placement and

layout of the PHY and corresponding support components.

PACKAGE LAYOUT

The LFCSP has an exposed pad underneath the package that

must be soldered to the PCB ground for mechanical, electrical,

and thermal reasons. For thermal impedance performance and to

maximize heat removal, the use of a 4 × 4 array of thermal vias

beneath the exposed ground pad is recommended. The PCB land

pattern must incorporate the exposed ground pad with these vias

in the footprint. The EVAL-ADIN1110EBZ uses an array of 4 × 4

filled vias on a 1.00 mm grid arrangement. The via pad diameter

dimension is 0.02 inches (0.5015 mm).

COMPONENT PLACEMENT AND ROUTING

Prioritization of the critical traces and components helps simplify

the routing exercise. Place and orient the critical traces and compo-

nents first to ensure an effective layout. The critical components

are the crystal and load capacitors, the CEXT_2 and DEXT_3

capacitors, and all bypass capacitors local to the ADIN1110 device.

Prioritize these components for placement and routing.

Follow these recommendations:

►

Place the decoupling capacitors as close as possible to their

respective input pin.

►

Minimize trace turns and use 45° corners.

►

Avoid traces crossing power planes on adjacent layers.

►

Avoid stubs.

►

Avoid vias on high speed signals. If vias are required, place

ground vias next to the signal vias to improve the return current

path.

CRYSTAL PLACEMENT AND ROUTING

Particular attention is required on the crystal placement and routing

to ensure minimum current consumption, reduce stray capacitance,

and improve noise immunity.

Follow these recommendations:

►

Place the crystal and its capacitors as close as possible to the

XTAL_I and XTAL_O pins.

►

Place the load capacitors close to each other.

►

Use a local GND plane (copper island) for the crystal and load

capacitor with a single point connection to the main GND.

►

Reduce parasitic capacitance by keeping the XTAL_I and

XTAL_O traces away from each other.

►

Adding a copper keep out on the layer beneath the crystal can

also reduce the parasitic capacitance.

PCB STACK

Follow these recommendations:

►

Use a PCB stack with a minimum of 4 layers.

►

Consider 6 layers or more with external layers used as ground

planes to improve EMI issues (optional).

►

Define copper layer thickness based on the application and

power requirements.

►

Use internal layers for power and ground planes.

►

Use external layers for signals.

►

Use via stitching to improve ground and reduce EMI. Stitching

pattern and via to via gaps to be defined based on the applica-

tion.

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