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ADIN1110CCPZ-R7 数据表(PDF) 63 Page - Analog Devices |
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ADIN1110CCPZ-R7 数据表(HTML) 63 Page - Analog Devices |
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63 / 104 page  Data Sheet ADIN1110 REGISTERS analog.com Rev. 0 | 63 of 104 P1 Rx Frames Dropped Due to FIFO Full Register Address: 0xAC, Reset: 0x00000000, Name: P1_RX_DROP_FULL_CNT Table 98. Bit Descriptions for P1_RX_DROP_FULL_CNT Bits Bit Name Description Reset Access [31:0] P1_RX_DROP_FULL_CNT Rx Frames Dropped Due to FIFO Full. Counts frames dropped due to a full receive FIFO. 0x0 R P1 Rx Frames Dropped Due to Filtering Register Address: 0xAD, Reset: 0x00000000, Name: P1_RX_DROP_FILT_CNT Table 99. Bit Descriptions for P1_RX_DROP_FILT_CNT Bits Bit Name Description Reset Access [31:0] P1_RX_DROP_FILT_CNT Rx Frames Dropped Due to Filtering. 0x0 R Frame Received on Port 1 with IFG Errors Register Address: 0xAE, Reset: 0x00000000, Name: P1_RX_IFG_ERR_CNT Table 100. Bit Descriptions for P1_RX_IFG_ERR_CNT Bits Bit Name Description Reset Access [31:0] P1_RX_IFG_ERR_CNT IFG Error Counter for Port 1 Received Frames. 0x0 R P1 Transmit Interframe Gap Register Address: 0xB0, Reset: 0x0000000B, Name: P1_TX_IFG Table 101. Bit Descriptions for P1_TX_IFG Bits Bit Name Description Reset Access [31:8] RESERVED Reserved. 0x0 R [7:0] P1_TX_IFG Interframe Gap. Generates an IFG of (P1_TX_IFG + 1) × 8 bit times between frames on Tx. 0xB R/W P1 MAC Loopback Enable Register Address: 0xB3, Reset: 0x00000000, Name: P1_LOOP Table 102. Bit Descriptions for P1_LOOP Bits Bit Name Description Reset Access [31:1] RESERVED Reserved. 0x0 R 0 P1_LOOPBACK_EN MAC Loopback. Enable loopback on the MII interface to the PHY. 0x0 R/W 0: normal operation, loopback disabled. 1: loopback enabled. P1 CRC Check Enable on Receive Register Address: 0xB4, Reset: 0x00000001, Name: P1_RX_CRC_EN Table 103. Bit Descriptions for P1_RX_CRC_EN Bits Bit Name Description Reset Access [31:1] RESERVED Reserved. 0x0 R |
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