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ADIN1110CCPZ-R7 数据表(PDF) 67 Page - Analog Devices |
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ADIN1110CCPZ-R7 数据表(HTML) 67 Page - Analog Devices |
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67 / 104 page  Data Sheet ADIN1110 REGISTERS analog.com Rev. 0 | 67 of 104 Table 113. Bit Descriptions for MI_STATUS Bits Bit Name Description Reset Access 5 MI_AN_COMPLETE Autonegotiation Complete. The autonegotiation complete bit indicates that the autonegotiation process is completed and the PHY link is up. Mirrors AN_COMPLETE. 0x0 R 4 MI_REM_FLT Remote Fault. The remote fault bit always reads as 0 as the PHY has no provision for remote fault detection. 0x0 R LH 3 MI_AN_ABLE Autonegotiation Ability. The autonegotiation ability bit always reads as 1 indicating that the PHY has the ability to perform autonegotiation. Mirrors AN_ABLE. 0x1 R 2 MI_LINK_STAT_LAT Link Status. This uses a latch low functionality as described in IEEE Standard 802.3 Subclause 45.2.7.20.5. If the link_status value is fail, this register remains cleared until the latching is cleared when the register is read. Mirrors AN_LINK_STATUS. 0x0 R LL 1 MI_JABBER_DET MII Jabber Detect. The jabber detect bit always reads as 0 as the 10BASE-T1L PHY does not incorporate a jabber detect function. 0x0 R LH 0 MI_EXT_CAPABLE MII Extended Capability. The extended capability bit always reads as 1 indicating that the PHY provides an extended set of capabilities that can be accessed through the extended register set. The extended register set consists of all of the management registers except 0, 1, and 15. 0x1 R PHY Identifier 1 Register Address: 0x2, Reset: 0x0283, Name: MI_PHY_ID1 The PHY Identifier 1 address allows 16 bits of the OUI to be observed. Table 114. Bit Descriptions for MI_PHY_ID1 Bits Bit Name Description Reset Access [15:0] MI_PHY_ID1 The PHY Identifier 1 address allows 16 bits of the OUI to be observed. 0x283 R PHY Identifier 2 Register Address: 0x3, Reset: 0xBC91, Name: MI_PHY_ID2 The PHY Identifier 2 address allows six bits of the OUI, the model number, and revision number to be observed. Table 115. Bit Descriptions for MI_PHY_ID2 Bits Bit Name Description Reset Access [15:10] MI_PHY_ID2_OUI OUI, Bits[7:2]. 0x2F R [9:4] MI_MODEL_NUM Model Number. 0x9 R [3:0] MI_REV_NUM Revision Number. 0x1 R MMD Access Control Register Address: 0xD, Reset: 0x0000, Name: MMD_ACCESS_CNTRL This address corresponds to the MMD access control register specified in Clause 22.2.4.3.11 of IEEE Standard 802.3-2018. Table 116. Bit Descriptions for MMD_ACCESS_CNTRL Bits Bit Name Description Reset Access [15:14] MMD_ACR_FUNCTION Function. The function register selects the type of MMD access on accesses to the MMD_DAR register. 0x0 R/W 00: address. 01: data, no post increment. 10: data, post increment on reads and writes. 11: data, and post increment on writes only. [13:5] RESERVED Reserved. 0x0 R |
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