ADIN1110CCPZ-R7 datasheet(12/104 Pages) AD

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Data Sheet

ADIN1110

THEORY OF OPERATION

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Rev. 0 | 12 of 104

The ADIN1110 is a low power, single port 10 Mb/s Ethernet MAC-

PHY device, compliant with the IEEE 802.3cg Ethernet standard for

long reach, 10 Mbps single pair Ethernet.

The ADIN1110 integrates the following features:

►

10BASE-T1L Ethernet PHY core and MAC with all the associat-

ed common analog circuitry

►

Input and output clock buffering

►

SPI and subsystem registers

►

Control logic to manage the reset and clock

►

Hardware configuration pins

►

Two configurable LED pins

POWER SUPPLY DOMAINS

The ADIN1110 has four power supply domains and requires a

minimum of one supply rail, as follows:

►

AVDD_H is the analog power supply input for the analog front

end (AFE) circuitry in the ADIN1110.

►

AVDD_L is the analog supply voltage for the internal LDO

circuits. AVDD_L can be connected to the AVDD_H rail when

in single supply mode, or to an alternative lower voltage rail

when the device is configured with dual supplies for lower power

consumption.

►

DVDD_1P1 is the 1.1 V digital core power supply input.

DVDD_1P1 can operate from an internal 1.1 V LDO output com-

ing from the DLDO_1P1 pin to the DVDD_1P1 pin. Alternatively,

DVDD_1P1 can be driven from an external 1.1 V supply for

greater power efficiency.

►

VDDIO enables the SPI voltage supply to be configured inde-

pendently of the other circuitry on the ADIN1110. VDDIO can be

connected directly to the AVDD_L rail.

In a single supply application, connect AVDD_H = AVDD_L =

VDDIO and use the internal 1.1 V LDO circuit for DVDD_1P1. The

appropriate supply voltage used depends on the end application

and cable length. For long reach/trunk applications, the higher

transmit amplitude of 2.4 V p-p requires AVDD_H = 3.3 V, whereas

spur applications can use a lower transmit amplitude of 1.0 V p-p

with an AVDD_H = 1.8 V.

MAC

The MAC included in the ADIN1110 supports 16 different MAC

addresses. The MAC also has one low priority receive first in, first

out (FIFO), one high priority receive FIFO and one transmit FIFO.

These FIFOs can ship data in store and forward mode when using

the generic SPI protocol, and in either store and forward or cut

through mode when using the OPEN Alliance protocol.

A generic version and OPEN Alliance version of the SPI protocol

are available. The data is transferred over the SPI half duplex using

the generic SPI protocol and full duplex using the OPEN Alliance

SPI protocol. See the MAC SPI section.

Interrupt (INT)

The ADIN1110 is capable of generating an interrupt to a host pro-

cessor using the INT pin in response to a variety of user selectable

conditions. The following conditions can be selected to generate an

interrupt:

►

Link status change

►

Port 1 receive FIFO receive data available

►

Frame transmit complete or transmit space available

►

Time stamp captured

►

Operation error detected

►

PHY related interrupts

When an interrupt occurs, the system can poll the MAC status

registers (STATUS0 and STATUS1) to determine the origin of the

interrupt.

AUTONEGOTIATION

The ADIN1110 uses the autonegotiation capability in accordance

with IEEE 802.3 Clause 98, providing a mechanism for exchanging

information between PHYs to allow link partners to agree to a

common mode of operation. During the autonegotiation process,

the PHY advertises its own capabilities and compares to those

received from the link partner. The concluded operating mode is

the transmit amplitude mode and master/slave preference common

across the two devices.

If a link is dropped, the autonegotiation process restarts automati-

cally. An autonegotiation restart can also be requested by writing

to the autonegotiation restart bit (AN_RESTART) in the autonego-

tiation control register.

The autonegotiation process takes some time to complete, depend-

ing on the number of pages exchanged, but is always the fastest

way to bring up a link. Clause 98 of the IEEE 802.3 standard details

the timers related to autonegotiation.

Note that autonegotiation is enabled by default for the ADIN1110,

and it is strongly recommended that autonegotiation is always

enabled.

Transmit Amplitude Resolution

Autonegotiation is used to resolve the transmit amplitude resolution.

The PHY can be configured to support both 1.0 V p-p and 2.4 V

p-p transmit levels or to operate with 1.0 V p-p transmit level only

through the hardware configuration (see Table 13). This configura-

tion can also be done in software using the 10BASE-T1L high level

transmit operating mode ability (AN_ADV_B10L_TX_LVL_HI_ABL)

and 10BASE-T1L high level transmit operating mode request

(AN_ADV_B10L_TX_LVL_HI_REQ) register bits.

To operate at 2.4 V p-p transmit level, both the local and remote

PHYs must advertise that they are capable of operating at 2.4

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