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ADIN1110CCPZ-R7 数据表(PDF) 85 Page - Analog Devices |
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ADIN1110CCPZ-R7 数据表(HTML) 85 Page - Analog Devices |
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85 / 104 page  Data Sheet ADIN1110 REGISTERS analog.com Rev. 0 | 85 of 104 Table 159. Bit Descriptions for AN_B10_ADV_ABILITY Bits Bit Name Description Reset Access 14 AN_B10_ADV_B10L_EEE 10BASE-T1L EEE Ability. This is a duplicate of the AN_ADV_B10L_EEE register. 0x0 R 13 AN_B10_ADV_B10L_TX_LVL_HI_ABL 10BASE-T1L High Level Transmit Operating Mode Ability. This is a duplicate of the AN_ADV_B10L_TX_LVL_HI_ABL register. Pin Dependent R/W 12 AN_B10_ADV_B10L_TX_LVL_HI_REQ 10BASE-T1L High Level Transmit Operating Mode Request. This is a duplicate of the AN_ADV_B10L_TX_LVL_HI_REQ register. Pin Dependent R/W [11:0] RESERVED Reserved. 0x0 R 10BASE-T1 Autonegotiation Status Register Device Address: 0x07; Register Address: 0x020F, Reset: 0x0000, Name: AN_B10_LP_ADV_ABILITY This address corresponds to the 10BASE-T1 autonegotiation status register specified in Clause 45.2.7.26 of Standard 802.3cg. Table 160. Bit Descriptions for AN_B10_LP_ADV_ABILITY Bits Bit Name Description Reset Access 15 AN_B10_LP_ADV_B10L 10BASE-T1L Ability. This is a duplicate of the AN_LP_ADV_B10L register. 0x0 R 14 AN_B10_LP_ADV_B10L_EEE 10BASE-T1L EEE Ability. This is a duplicate of the AN_LP_ADV_B10L_EEE register. 0x0 R 13 AN_B10_LP_ADV_B10L_TX_LVL_HI_ABL 10BASE-T1L High Level Transmit Operating Mode Ability. This is a duplicate of the AN_LP_ADV_B10L_TX_LVL_HI_ABL register. 0x0 R 12 AN_B10_LP_ADV_B10L_TX_LVL_HI_REQ 10BASE-T1L High Level Transmit Operating Mode Request. This is a duplicate of the AN_LP_ADV_B10L_TX_LVL_HI_REQ register. 0x0 R [11:8] RESERVED Reserved. 0x0 R 7 AN_B10_LP_ADV_B10S_FD Link Partner 10BASE-T1S Full Duplex Ability. This is a duplicate of the AN_LP_ADV_B10S_FD register. 0x0 R 6 AN_B10_LP_ADV_B10S_HD Link Partner 10BASE-T1S Half-Duplex Ability. This is a duplicate of the AN_LP_ADV_B10S_HD register. 0x0 R [5:0] RESERVED Reserved. 0x0 R Autonegotiation Force Mode Enable Register Device Address: 0x07; Register Address: 0x8000, Reset: 0x0000, Name: AN_FRC_MODE_EN Note that the effect of this register is superseded by the AN_EN bit, which enables the autonegotiation process. If autonegotiation is disabled (AN_EN = 0) and AN_FRC_MODE_EN is 1, forced mode is enabled. Table 161. Bit Descriptions for AN_FRC_MODE_EN Bits Bit Name Description Reset Access [15:1] RESERVED Reserved. 0x0 R 0 AN_FRC_MODE_EN Autonegotiation Forced Mode. Enables forced mode functionality. 0x0 R/W Extra Autonegotiation Status Register Device Address: 0x07; Register Address: 0x8001, Reset: 0x0000, Name: AN_STATUS_EXTRA This register is provided in addition to AN_STATUS. Table 162. Bit Descriptions for AN_STATUS_EXTRA Bits Bit Name Description Reset Access [15:11] RESERVED Reserved. 0x0 R |
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