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ADP5056

Data Sheet

Rev. 0 | Page 28 of 31

DESIGN EXAMPLE

This section provides an example of the step by step design

procedures and the external components required for Channel 1.

Table 9 lists the design requirements for this example.

Table 9. Example Design Requirements for Channel 1

Parameter

Specification

Input Voltage

VPVIN1 = 12 V ± 5%

Output Voltage

VOUT1 = 1.2 V

Output Current

IOUT1 = 7 A

Output Ripple

ΔVOUT1_RIPPLE = 12 mV in CCM mode

Load Transient

±5% at 25% to 75% load transient, 1 A/μs

Although this example shows step by step design procedures for

Channel 1, the procedures apply to all other buck regulator

channels (Channel 1 to Channel 3).

SETTING THE SWITCHING FREQUENCY

The first step is to determine the switching frequency for the

ADP5056 design. In general, higher switching frequencies

produce a smaller solution size due to the lower component

values required, whereas lower switching frequencies result in

higher conversion efficiency due to lower switching losses.

The switching frequency of the ADP5056 can be set to a value from

250 kHz to 2500 kHz by connecting a resistor from the RT pin to

ground. The selected resistor allows the user to make decisions

based on the trade-off between efficiency and solution size.

However, the highest supported switching frequency must be

assessed by checking the voltage conversion limitations enforced

by the minimum on time and the minimum off time (see the

Voltage Conversion Limitations section).

In this design example, a switching frequency of 600 kHz is

used to achieve an optimal combination of small solution size

and high conversion efficiency. To set the switching frequency

to 600 kHz and calculate the value of the resistor from the RT

pin to ground, RT, use the following equations:



0.998

167,305

kΩ =

kHz



0.998

167,305

kΩ =

= 280 kΩ

600

Therefore, select the closest standard 1% resistor value for RT =

280 kΩ.

SETTING THE OUTPUT VOLTAGE

Select a 10 kΩ bottom resistor (RBOT) and then calculate the top

feedback resistor by using the following equation:

RBOT = RTOP × (VREF/(VOUT − VREF))

where VREF is 0.6 V for Channel 1.

To set the output voltage to 1.2 V, choose the following resistor

values: RTOP = 10 kΩ, RBOT = 10 kΩ.

SETTING THE CONFIGURATIONS (CFG1 AND CFG2)

The CFG1 pin can program the load output capability and parallel

operation for all channels. For this example, choose RCFG1 = 0 Ω

(see Table 6).

The CFG2 pin can program the tSET timer (2.6 ms or 20.8 ms),

fast transient functionality, and sequence for the ADP5056. For

this example, choose RCFG2 = 0 Ω (see Table 7).

SELECTING THE INDUCTOR

The peak-to-peak ΔIL is set to 35% of the maximum output

current. Use the following equation to estimate the value of the

inductor:

L = ((VIN − VOUT) × D)/(ΔIL × fSW)

where:

VIN = 12 V.

VOUT = 1.2 V.

D is the duty cycle (D = VOUT/VIN = 0.1).

ΔIL = 35% × 7 A = 2.45 A.

fSW = 600 kHz.

The resulting value for L is 0.73 μH. The closest standard inductor

value is 0.8 μH. Therefore, ΔIL is 2.25 A.

Calculate the peak inductor current by using the following

equation:

IPEAK = IOUT + (ΔIL/2)

The calculated peak current for the inductor is 8.125 A.

Use the following equation to calculate the rms current of the

inductor:

RMS

OUT





The rms current of the inductor is approximately 7.03 A.

Therefore, an inductor with a minimum rms current rating of

7.03 A and a minimum saturation current rating of 8.125 A is

required. However, to prevent the inductor from reaching the

saturation point in current-limit conditions, it is recommended

that the inductor saturation current be higher than the maximum

peak current limit, typically 11.65 A, for reliable operation.

Based on these requirements and recommendations, the

XAL5030-801ME, with a dc resistance of 5.14 mΩ, was selected

for this design.

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