Data Sheet

ADP5056

Rev. 0 | Page 9 of 31

Pin No.

Mnemonic

Description

22

PWRGD

Power Good Output for Selective Channels.

23

EN2

Enable Input for Channel 2.

24

COMP2

Error Amplifier Output for Channel 2. Connect an RC network from this pin to ground.

25

FB2

Feedback Sensing Input for Channel 2.

26

RAMP2

Slope Compensation Setting for Channel 2. Connect a resistor from RAMP2 to ground to set the slope compensation.

27

CFG2

mode, and sequence mode.

28

CFG1

System Configuration Pin 1. Connect one resistor from this pin to ground to program the current limit, parallel

operation, and clock output settings.

29

PVIN2

Power Input for Channel 2.

30

PVIN2

Power Input for Channel 2.

31

PVIN2

Power Input for Channel 2.

32

SW2

Switching Node Output for Channel 2.

33

SW2

Switching Node Output for Channel 2.

34

SW2

Switching Node Output for Channel 2.

35

PGND

Power Ground for all Channels.

36

PGND

Power Ground for all Channels.

37

PGND

Power Ground for all Channels.

38

SW1

Switching Node Output for Channel 1.

39

SW1

Switching Node Output for Channel 1.

40

SW1

Switching Node Output for Channel 1.

41

PVIN1

Power Input for Channel 1.

42

PVIN1

Power Input for Channel 1.

43

PVIN1

Power Input for Channel 1.