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ADP5056ACCZ-R7 数据表(PDF) 4 Page - Analog Devices |
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ADP5056ACCZ-R7 数据表(HTML) 4 Page - Analog Devices |
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4 / 31 page  ADP5056 Data Sheet Rev. 0 | Page 4 of 31 SPECIFICATIONS Input voltage (VIN) = bias input voltage (VBIAS) = 12 V, VREG voltage (VREG) = 4.8 V, TJ = −40°C to +150°C for minimum and maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments WIDE INPUT VOLTAGE RANGE VIN 2.75 18 V PVIN1 pin, PVIN2 pin, PVIN3 pin BIAS INPUT VOLTAGE RANGE VBIAS 4.5 18 V VBIAS pin QUIESCENT CURRENT VBIAS pin Operating Quiescent Current IQ(3-BUCKS) 6.2 7.5 mA No switching, all ENx pins high Shutdown Current of Three Channels ISHDN(3-BUCKS) 42 80 µA All ENx pins low UNDERVOLTAGE LOCKOUT Power Input UVLOPVINx PVIN1 pin, PVIN2 pin, PVIN3 pin Rising Threshold VUVLO1-RISING 2.5 2.75 V Falling Threshold VUVLO1-FALLING 2.22 V Hysteresis VHYS1 0.30 V Bias Input Voltage UVLOVBIAS VBIAS pin Rising Threshold VUVLO2-RISING 4.20 4.50 V Falling Threshold VUVLO2-FALLING 3.60 3.80 V Hysteresis VHYS2 0.40 V OSCILLATOR CIRCUIT Switching Frequency fSW 530 600 630 kHz RT = 280 kΩ 1140 1200 1250 kHz RT = 140 kΩ 1700 1800 1900 kHz RT = 94.2 kΩ Switching Frequency Range 250 2500 kHz Synchronization Input Input Clock Range fSYNC 250 2700 kHz Input Clock Pulse Width Minimum On Time tSYNC_MIN_ON 100 ns Minimum Off Time tSYNC_MIN_OFF 100 ns Input Clock High Voltage VH(SYNC) 2.65 V Input Clock Low Voltage VL(SYNC) 1.2 V Synchronization Output Clock Frequency fCLK fSW kHz Positive Pulse Duty Cycle tCLK_PULSE_DUTY 50 % Rise or Fall Time tCLK_RISE_FALL 2 ns High Level Voltage VH(SYNC_OUT) VREG V PRECISION ENABLING EN1 pin, EN2 pin, EN3 pin Enable Voltage Range VEN_RANGE 0 18 V High Level Threshold VTH_H(EN) 0.615 0.67 V Low Level Threshold VTH_L(EN) 0.52 0.575 V Source Current (High Level) ITH_H(EN) 0.48 0.9 1.55 µA Above the rising threshold Source Current (Low Level) ITH_L(EN) 2.0 3.5 6.0 µA Below the falling threshold POWER GOOD Rising High Threshold VPWRGD(RISE_H) 105 % Rising Low Threshold VPWRGD(RISE_L) 95 % Falling High Threshold VPWRGD(FALL_H) 107 % Falling Low Threshold VPWRGD(FALL_L) 93 % Internal Power-Good Hysteresis VPWRGD(HYS) 2 % Falling Delay for PWRGD Pin tPWRGD_FALL_DLY 4 × switching period (tSW) ms Rising Delay for PWRGD Pin1 tPWRGD_RISE_DLY 0 or tSET ms tSET = 2.6 ms when the resistor value on the CFG2 pin (RCFG2) = 0 Ω |
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