ADP5056

Data Sheet

Rev. 0 | Page 8 of 31

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

28

27

26

25

24

23

22

21

20

CFG1

CFG2

RAMP2

FB2

COMP2

EN2

PWRGD

COMP3

FB3

GND

GND

RAMP1

FB1

COMP1

RT

EN1

GND

VREG

ADP5056

TOP VIEW

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

GND

This pin is for internal test purposes. Connect this pin to ground.

2

GND

This pin is for internal test purposes. Connect this pin to ground.

3

RAMP1

Slope Compensation Setting for Channel 1. Connect a resistor from RAMP1 to ground to set the slope compensation.

4

FB1

Feedback Sensing Input for Channel 1.

5

COMP1

Error Amplifier Output for Channel 1. Connect a resistance and capacitor (RC) network from this pin to ground.

6

RT

Frequency Setting. Connect a resistor from RT to ground to program the switching frequency.

7

EN1

Enable Input for Channel 1.

8

GND

Analog Ground.

9

VREG

Output of the Internal 4.8 V Regulator. The control circuitry is powered from this voltage on this pin. Place a 4.7 μF

ceramic capacitor (X7R or X5R) between this pin to GND.

10

VBIAS

Bias Input Voltage Pin to Supply Internal Regulator.

11

SYNC/MODE

Synchronization Input/Output (SYNC). To synchronize the switching frequency of the device to an external clock,

connect this pin to an external clock with a frequency from 250 kHz to 2700 kHz. This pin can also be configured

as a synchronization output via the CFG1 pin configuration.

FPWM or Automatic PWM/PSM Selection Pin (MODE). When this pin is logic high, each channel works in FPWM

mode. When this pin is logic low, all channels operate in automatic PWM/PSM mode.

12

BST1

Supply Rail for the High-Side Gate Drive in Channel 1. Place a 0.1 μF capacitor (X7R or X5R) between SW1 and BST1.

13

BST3

Supply Rail for the High-Side Gate Drive in Channel 3. Place a 0.1 μF capacitor (X7R or X5R) between SW3 and BST3.

14

PGND

Power Ground for all Channels.

15

SW3

Switching Node Output for Channel 3.

16

PVIN3

Power Input for Channel 3.

17

BST2

Supply Rail for the High-Side Gate Drive in Channel 2. Place a 0.1 μF capacitor (X7R or X5R) between SW2 and BST2.

18

EN3

Enable Input for Channel 3.

19

RAMP3

Slope Compensation Setting for Channel 3. Connect a resistor from RAMP3 to ground to set the slope compensation.

20

FB3

Feedback Sensing Input for Channel 3.

21

COMP3

Error Amplifier Output for Channel 3. Connect an RC network from this pin to ground.