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ADP5056

Data Sheet

Rev. 0 | Page 14 of 31

THEORY OF OPERATION

The ADP5056 is a power management unit that combines three

high performance buck regulators in a 43-terminal LGA package

to meet demanding performance and board space requirements.

The device enables direct connection to high input voltages up

to 18 V with no preregulators to make applications simpler and

more efficient.

BUCK REGULATOR OPERATIONAL MODES

PWM Mode

In PWM mode, the buck regulators in the ADP5056 operate at a

fixed frequency. An internal oscillator programmed by the RT

pin sets this frequency. The ADP5056 uses the low-side MOSFET

current for the PWM control, as shown in Figure 28. The valley

current information is captured at the end of the off period and

combines with the slope ramp to form the emulated current ramp

voltage. The resistor from the RAMPx pin to ground controls the

slope ramp voltage. At the start of each oscillator cycle, the high-

side MOSFET turns on, and the inductor current increases until

the emulated current ramp voltage crosses the COMPx voltage.

When the current ramp voltage crosses the COMPx voltage, it

turns off the high-side MOSFET and turns on the low-side

MOSFET, which in turn places a negative voltage across the

inductor, causing a reduction in the inductor current. The low-

side MOSFET stays on for the remainder of the cycle.

PVINx

RRAMP

CRAMP

CLK

S Q

IN DH

ACS*

PWM

PVINx

VOUT

COUT

0.6V

VCOMP

RTOP

RBOT

IRAMP

VRAMP

CS IS THE CURRENT SENSING AMPLIFIER.

Figure 28. FlexMode™ PWM Control Architecture

PSM Mode

To achieve higher efficiency at light loads, the buck regulators in

the ADP5056 smoothly transition to variable frequency PSM

operation when the output load falls below the PSM current

threshold. When the output voltage (VOUT) falls below regulation,

the buck regulator enters PWM mode for a few oscillator cycles

until the voltage increases to within regulation. During the idle

time between bursts, the MOSFET turns off, and the output

capacitor supplies all the output current.

The PSM comparator monitors the internal compensation node,

which represents the peak inductor current information. The

average PSM current threshold depends on the VIN, the VOUT, the

inductor, and the output capacitor. Because the output voltage

occasionally falls below regulation and then recovers, the output

voltage ripple in PSM operation is larger than the ripple in the

FPWM mode of operation under light load conditions.

FPWM and Automatic PWM/PSM Modes

The buck regulators can be configured to always operate in

FPWM mode using the SYNC/MODE pin. In FPWM mode, the

regulator continues to operate at a fixed frequency even when the

output current is below the PWM/PSM threshold. In FPWM

mode, efficiency is lower compared to PSM mode under light

load conditions. The low-side MOSFET remains on when the

inductor current falls to less than 0 A, causing the ADP5056 to

enter continuous conduction mode (CCM).

The buck regulators can be configured to operate in automatic

PWM/PSM mode using the SYNC/MODE pin. In automatic

PWM/PSM mode, the buck regulators operate in either PWM

mode or PSM mode, depending on the output current. When

the average output current falls below the PWM/PSM threshold,

the buck regulator enters PSM mode operation. In PSM mode,

the regulator operates with a reduced switching frequency to

maintain high efficiency. The low-side MOSFET turns off when

the inductor current reaches 0 A, causing the regulator to operate

in discontinuous mode (DCM).

The user can alternate between FPWM mode and automatic

PWM/PSM mode during operation. The flexible configuration

capability during operation of the device enables efficient power

management.

When a logic low level is applied to the SYNC/MODE pin, the

operational mode of all three buck regulators is automatic

PWM/PSM mode. When a logic high level is applied to the

SYNC/MODE pin, the operational mode of all three buck

regulators is FPWM mode.

ADJUSTABLE OUTPUT VOLTAGES

The ADP5056 provides an adjustable output voltage via an external

resistor divider. For the adjustable output settings, use an external

resistor divider to set the desired output voltage via the feedback

reference voltage. The default reference voltage on each feedback

pin is 600 mV for each channel.

INTERNAL REGULATORS (VREG)

The internal VREG regulator in the ADP5056 provides a stable

4.8 V power supply for the internal circuitry. Connect a 4.7 µF

(X5R or X7R) ceramic capacitor between VREG and ground. The

internal VREG regulator is always active as long as the VBIAS

voltage is available.

SEPARATE SUPPLY APPLICATIONS

The ADP5056 supports separate input voltages for the three buck

regulators, meaning that the input voltages for the three buck

regulators can connect to different supply voltages. The

ADP5056 integrates 100 nF, 25 V, X8L ceramic capacitors to

provide local decoupling from PVIN1 and PVIN2 to power

ground in Channel 1 and Channel 2.

The VBIAS voltage provides the power supply for the internal

regulators and the control circuitry. Therefore, if the user plans

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