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ADP5056ACCZ-R7 数据表(PDF) 24 Page - Analog Devices |
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ADP5056ACCZ-R7 数据表(HTML) 24 Page - Analog Devices |
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24 / 31 page ![]() ADP5056 Data Sheet Rev. 0 | Page 24 of 31 POWER DISSIPATION The total power dissipation in the ADP5056 simplifies to PD = PBUCK1 + PBUCK2 + PBUCK3 where: PD is the power dissipation in the package. PBUCK1 is the power dissipation of Channel 1. PBUCK2 is the power dissipation of Channel 2. PBUCK3 is the power dissipation of Channel 3. Buck Regulator Power Dissipation The power dissipation (PLOSS) for each buck regulator includes power switch conduction losses (PCOND), switching losses (PSW), and transition losses (PTRAN). Other sources of power dissipation exist, but these sources are generally less significant at the high output currents of the application thermal limit. Use the following equation to estimate the power dissipation of the buck regulator: PLOSS = PCOND + PSW + PTRAN Power Switch Conduction Loss (PCOND) Power switch conduction losses are caused by the flow of output current through both the high-side and low-side power switches. Each of these switches has internal on resistance (RDSON). Use the following equation to estimate the power switch conduction loss: PCOND = (RDSON_HS × D + RDSON_LS × (1 − D)) × IOUT2 where: RDSON_HS is the on resistance of the high-side MOSFET. RDSON_LS is the on resistance of the low-side MOSFET. Switching Loss (PSW) Switching losses are associated with the current drawn by the driver to turn the power devices on and off at the switching frequency. Each time a power device gate is turned on or off, the driver transfers a charge from the input supply to the gate, and then from the gate to ground. Use the following equation to estimate the switching loss: PSW = (CGATE_HS + CGATE_LS) × VIN2 × fSW where: CGATE_HS is the gate capacitance of the high-side MOSFET. CGATE_LS is the gate capacitance of the low-side MOSFET. Transition Loss (PTRAN) Transition losses occur because the high-side MOSFET cannot turn on or off instantaneously. During a switch node transition, the MOSFET provides all the inductor current. The source to drain voltage of the MOSFET is half the input voltage, resulting in power loss. Transition losses increase with both load and input voltage and occur twice for each switching cycle. Use the following equation to estimate the transition loss: PTRAN = 0.5 × VIN × IOUT × (tR + tF) × fSW where: tR is the rise time of the switch node. tF is the fall time of the switch node. JUNCTION TEMPERATURE The junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to power dissipation, as shown in the following equation: TJ = TA + TR where: TJ is the junction temperature. TA is the ambient temperature. TR is the rise in temperature of the package due to power dissipation. The rise in temperature of the package is directly proportional to the power dissipation in the package. The proportionality constant for this relationship is the thermal resistance from the junction of the die to the ambient temperature, as shown in the following equation: TR = θJA × PD where: θJA is the thermal resistance from the junction of the die to the ambient temperature of the package (see Table 4). An important factor to consider is that the thermal resistance value is based on a 4-layer, 4 inch × 3 inch PCB with 2.5 oz. of copper, as specified in the JEDEC standard, whereas real-world applications may use PCBs with different dimensions and a different number of layers. It is important to maximize the amount of copper used to remove heat from the device. Copper exposed to air dissipates heat better than copper used in the inner layers. Connect Pin 35, Pin 36, and Pin 37 to the ground plane with the maximum number of vias. |
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