ADP5056ACCZ-R7 datasheet(18/31 Pages) AD

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ADP5056

Data Sheet

Rev. 0 | Page 18 of 31

PARALLEL OPERATION

The ADP5056 supports 2-phase parallel operation of Channel 1

and Channel 2 to provide a single output with up to 14 A of

current. The ADP5056 includes two different parallel operation

modes via the CFG1 pin configuration: in phase parallel operation

and interleaved parallel operation.

In Phase Parallel Operation

In phase parallel operation parallels internal MOSFETs and driver

circuitry between Channel 1 and Channel 2. In phase parallel

operation treats Channel 1 as the control master, and the Channel

2 control stage is ignored. The in phase parallel operation mode

uses a single inductor for external components and space saving. To

configure Channel 1 and Channel 2 for in phase parallel single

output operation, do the following (see Figure 37):



Use the CFG1 pin to select in phase parallel operation, as

specified in Table 6.



Use the COMP1 pin as the compensation network.



Use the FB1 pin to set the output voltage.



Use the EN1 pin to enable the channel.



Connect the FB2 pin to ground (FB2 is ignored).



Leave the COMP2 pin open (COMP2 is ignored).



Leave the RAMP2 pin open (RAMP2 is ignored).



Connect the EN2 pin to ground (EN2 is ignored).

CHANNEL 1

BUCK

(7A)

CHANNEL 2

BUCK

(7A)

FB1

PVIN1

VIN

EN1

EN2

COMP1

SW1

FB2

SW2

PVIN2

COMP2

CFG1

VOUT1

(UP TO 14A)

PGND

RAMP1

RAMP2

Figure 37. In Phase Parallel Operation for Channel 1 and Channel 2

Interleaved Parallel Operation

The ADP5056 supports 2-phase interleaved parallel operation of

Channel 1 and Channel 2 to provide a single output with up to

14 A of current. In this mode, two channels operate in 180° out

of phase operation and rely on an individual control loop to achieve

current balance between the two channels. The interleaved parallel

operation mode uses two inductors with the advantages of ripple

current cancellation and higher equivalent switching frequency.

To configure a two-phase interleaved parallel operation, do the

following (see Figure 38):



Use the CFG1 pin to select interleaved parallel operation,

as specified in Table 6.



Use the COMP1 pin as the compensation network.



Use the same RAMP1 and RAMP2 resistors.



Use the FB1 pin to set the output voltage.



Use the EN1 pin to enable the channel.



Connect the FB2 pin to ground (FB2 is ignored).



Leave the COMP2 pin open (COMP2 is ignored).



Connect the EN2 pin to ground (EN2 is ignored).

CHANNEL 1

BUCK

(7A)

CHANNEL 2

BUCK

(7A)

FB1

PVIN1

VIN

EN1

EN2

COMP1

SW1

FB2

SW2

PVIN2

COMP2

CFG1

VOUT1

(UP TO 14A)

RAMP2

PGND

RAMP1

Figure 38. Interleaved Parallel Operation for Channel 1 and Channel 2

The current balance in parallel configuration is well balanced

by careful designs of symmetrical printed circuit board (PCB)

layout and circuitry designs. Figure 39 and Figure 40 show the

typical current balance matching in the parallel output

configuration.

CH1 5.0V/DIV

1MΩ BW: 20.0M

CH2 5.0V/DIV

1MΩ BW: 20.0M

CH3 2.0A/DIV

50Ω

W:20.0M

CH4 2.0A/DIV

50Ω

W:20.0M

2.0µs/DIV 50.0MS/s

A CH1

800mV

20.0ns/pt

Figure 39. Steady State Waveform in Interleaved Parallel Output

Configuration, VIN = 12 V, VOUT = 1.2 V, fSW = 600 kHz, FPWM Mode,

Channel 1 = SW1, Channel 2 = SW2, Channel 3 = Current of Inductor L1,

Channel 4 = Current of Inductor L2

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