ADP5056ACCZ-R7 datasheet(15/31 Pages) AD

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Data Sheet

ADP5056

Rev. 0 | Page 15 of 31

to use separate supply voltages for the buck regulators, the VBIAS

voltage must be greater than the UVLO threshold before the

other channels begin to operate.

Precision enabling can monitor the voltages of the PVIN1 pin,

the PVIN2 pin, and the PVIN3 pin and to delay the startup of

the outputs to ensure that the voltages of the PVIN1 pin, the

PVIN2 pin, and the PVIN3 pin are high enough to support the

outputs in regulation. For more information, see the Precision

Enabling section.

The ADP5056 supports cascading supply operation for the three

buck regulators. As shown in Figure 29, PVIN2 and PVIN3 are

powered from the Channel 1 output. In this configuration, the

Channel 1 output voltage must be higher than the UVLO

threshold for PVIN2 and PVIN3.

PVIN1

BUCK CHANNEL 1

BUCK CHANNEL 2

VOUT1

PVIN2 TO

PVIN3

VOUT2 TO

VOUT3

VIN

VBIAS

Figure 29. Cascading Supply Application

BOOTSTRAP CIRCUITRY

Each buck regulator in the ADP5056 has an integrated bootstrap

regulator. The bootstrap regulator requires a 0.1 μF ceramic

capacitor (X5R or X7R) between the BSTx pins and SWx pins to

provide the gate drive voltage for the high-side MOSFET.

ACTIVE OUTPUT DISCHARGE SWITCH

Each buck regulator in the ADP5056 integrates a discharge switch

from the switching node to ground. This switch is turned on when

the associated regulator is disabled, which helps to discharge the

output capacitor quickly. The typical value of the discharge switch

is 85 Ω for Channel 1 to Channel 3.

PRECISION ENABLING

The ADP5056 has an enable control pin for each regulator. The

enable control pin (ENx) features a precision enable circuit with

a 0.615 V reference voltage. When the voltage at the ENx pin is

greater than 0.615 V (typical high level threshold), the regulator

is enabled. When the ENx pin voltage falls below 0.575 V

(typical low level threshold), the regulator is disabled. The

ADP5056 turns off the low-side MOSFET only after the

inductor current reaches zero.

The precision enable pin has an internal pull-down current

source (3.5 μA) that provides a default turn-off when the enable

pin is left open. When the enable pin exceeds 0.615 V (typical),

the regulator is enabled and the internal pull-down current source

at the enable pin decreases to 0.9 μA. The precision enabling uses

the ratio of the external resistor divider to program the UVLO

threshold to monitor either input voltage or output voltage,

while using the absolute value of the external resistor divider to

program the hysteresis window. For more information, see the

Programming the UVLO Input section.

To force the regulator to automatically start up when input power is

applied, connect the enable pin to the VREG pin.

0.615V

0.9µA

2.6µA

EN_CMP

–

PVINx

ENx

RTOP_EN

RBOT_EN

Figure 30. Precision Enable Diagram for One Channel

SEQUENCE MODE

The ADP5056 integrates the sequence control on each channel.

When the ENx signal goes high, each channel controlled by the

sequencer begins a soft start after the delay time (tEN_DLYx) specified

by the CFG2 pin setting (see Table 7). Similarly, when the ENx

signal goes low, the channel turns off after the delay timer

(tDIS_DLYx). The turn on and turn off delay timer for all channels is

designed in an opposite manner to meet typical system sequence

requirements. The turn-on delay step is 3 × tSET timer, and the turn-

off delay step is 6 × tSET timer, which provides the output with

extra discharge time. The tSET timer can be set to 2.6 ms or

20.8 ms by the CFG2 pin configuration. For example, when the

CFG2 pin connects to 14.3 kΩ, the start-up sequence is set as

Channel 1, Channel 2, and Channel 3. The enable delay of

Channel 1, Channel 2, and Channel 3 are 0 ms, 7.8 ms, and

15.6 ms. The shutdown sequence is set as Channel 3, Channel 2,

and Channel 1. The disable delay of Channel 1, Channel 2, and

Channel 3 are 31.2 ms, 15.6 ms, and 0 ms. Figure 31 shows the

logical states of each channel controlled by the grouped ENx

signal, and it does not show soft start and output discharge ramps.

ENx

CHANNEL x

OFF

tDIS_DLYx

tEN_DLYx

Figure 31. Sequencer Mode

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