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ADP5056ACCZ-R7 数据表(PDF) 3 Page - Analog Devices |
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ADP5056ACCZ-R7 数据表(HTML) 3 Page - Analog Devices |
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3 / 31 page  Data Sheet ADP5056 Rev. 0 | Page 3 of 31 FUNCTIONAL BLOCK DIAGRAM RT SYNC/MODE DIGITAL DECODER CFG1 CFG2 VBIAS VREG INTERNAL REGULATOR (POR, UVLO) GND GND VREG POWER-ON RESET PWRGD HOUSEKEEPING LOGIC + – Q1 UVLO1 PVIN1 SW1 BST1 VREG VREG PGND CONTROL LOGIC AND MOSFET DRIVER WITH ANTICROSS PROTECTION EN1 0.615V HICCUP AND LATCH-UP + – OCP COMP1 FB1 CLK1 ZERO CROSS + – + – CHANNEL 1 – BUCK DUPLICATE CHANNEL 1 CHANNEL 2 – BUCK EN2 COMP2 FB2 PGND PVIN2 SW2 BST2 + – EA1 CMP1 Q2 DUPLICATE CHANNEL 1 CHANNEL 3 – BUCK EN3 COMP3 FB3 PGND PVIN3 SW3 BST3 0.9µA 2.6µA RAMP1 + – ACS1* ICS ICS 107% × VREF VREF CLK1 100nF 25V RAMP2 RAMP3 ½ × PVIN1 CLK2 CLK3 GND OSCILLATOR SLOPE COMP + – 93% × VREF DRIVER DRIVER 100nF 25V *ACS1 IS THE CURRENT SENSING AMPLIFIER OF CHANNEL 1. Figure 2. |
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