ADP5056ACCZ-R7 datasheet(19/31 Pages) AD

19 / 31 page

Data Sheet

ADP5056

Rev. 0 | Page 19 of 31

10 11

14 15

TOTAL OUTPUT CURRENT [A]

IDEAL

CH1

CH2

Figure 40. Current Balance in Interleaved Parallel Output Configuration,

VIN = 12 V, VOUT = 1.2 V, fSW = 600 kHz, FPWM Mode

FAST TRANSIENT MODE

The ADP5056 includes fast transient response for large load

step conditions. The ADP5056 feedback pin senses the output

voltage to determine if a load step has occurred. When the output

voltage falls below the specific threshold, the internal loop gain

gradually increases to improve the load transient response

speed. The fast enhanced transient threshold is at −2.5% × VOUT

with five times of nominal gM, where gM = 350 μA/V.

The CFG2 pin needs be programmable to turn on the fast

transient mode.

CH1 50.0mV/DIV

W:20.0M

CH4 2.0A/DIV

50Ω BW:20.0M

51.5mV/DIV 100µs

100µs/DIV 50MS/s

A CH4

3.04A

20.0ns/pt

Figure 41. Enable or Disable Fast Transient Mode, Load Transient

Comparison, VIN = 12 V, VOUT = 1.2 V, fSW = 600 kHz, FPWM Mode,

Channel 1 = VOUT with Fast Transient Mode Enable, Channel 3 = VOUT with

Fast Transient Mode Enable, Channel 4 = IOUT

STARTUP WITH PRECHARGED OUTPUT

The buck regulators in the ADP5056 include a precharged start-up

feature to protect the low-side FETs from damage during

startup. If the output voltage is precharged before the regulator

is turned on, the regulator prevents reverse inductor current

(which discharges the output capacitor) until the internal soft

start reference voltage exceeds the precharged voltage on the

feedback (FBx) pin.

CH1 500mV/DIV 1MΩ BW: 20M

CH2 5.0V/DIV

1MΩ BW: 20M

CH3 2.0V/DIV

1MΩ BW: 20M

CH4 1.0A/DIV

50Ω BW: 500M

20.0ms/DIV 500kS/s

A CH1

870mV

2.0µs/pt

Figure 42. Channel 1 Startup with Precharged Ouput, VIN = 12 V, VOUT = 1.2 V,

fSW = 600 kHz, FPWM Mode, Channel 1 = VOUT, Channel 2 = EN,

Channel 3 = PWRGD, Channel 4 = IOUT

CURRENT-LIMIT PROTECTION

The ADP5056 uses the emulated current ramp voltage for cycle by

cycle current-limit protection to prevent current runaway. When

the emulated current ramp voltage reaches the valley current-

limit threshold plus the ramp voltage, the high-side MOSFET

turns off and the low-side MOSFET turns on until the next

cycle. If the overcurrent counter reaches 20, the device enters

hiccup mode, and the ADP5056 turns off the low-side MOSFET

only after the inductor current reaches zero. During hiccup

mode, the high-side MOSFET and low-side MOSFET are both

turned off. The device remains in this mode for seven soft start

cycles and then attempts to restart with soft start. If the current-

limit fault is cleared, the device resumes normal operation.

Otherwise, the device re-enters hiccup mode.

PVINx

RRAMP

CRAMP

SWx

VFB

PWM

IRAMP

VRAMP

CYCLE-BY-CYCLE

THRESHOLD

CURRENT-LIMIT

COMPARATOR

HICCUP

CONTROL

BLOCK

ACS*

*ACS IS THE CURRENT SENSING AMPLIFIER.

Figure 43. Current-Limit Circuitry

The buck regulators in the ADP5056 include negative current-

limit protection circuitry to limit certain amounts of negative

current flowing through the low-side MOSFET switch and

high-side MOSFET body diode.

ADP5056ACCZ-R7 数据表(PDF) 19 Page - Analog Devices

ADP5056ACCZ-R7 数据表(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

数据表下载