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EDB8164B4PR-1DATF-R 数据表(PDF) 38 Page - Micron Technology |
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EDB8164B4PR-1DATF-R 数据表(HTML) 38 Page - Micron Technology |
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38 / 152 page ![]() Table 27: MR6 Basic Configuration 2 (MA[7:0] = 06h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Revision ID1 (Die Revision) Note: 1. MR6 is vendor-specific. Table 28: MR6 Op-Code Bit Definitions Feature Type OP Definition Revision ID1 (Die Revision) Read-only OP[7:0] 0000 0000b: Version A 0000 0001b: Version B 0000 0010b: Version C 0000 0010b: Version D(512Mb only) 0000 0011b: Version D Table 29: MR7 Basic Configuration 3 (MA[7:0] = 07h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Revision ID2 (RFU) Table 30: MR7 Op-Code Bit Definitions Feature Type OP Definition Revision ID2 (RFU) Read-only OP[7:0] 0000 0000b: Default Value Note: 1. MR7 is vendor-specific. Table 31: MR8 Basic Configuration 4 (MA[7:0] = 08h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 I/O width Density Type Table 32: MR8 Op-Code Bit Definitions Feature Type OP Definition Type Read-only OP[1:0] 00b: S4 SDRAM 01b: S2 SDRAM 10b: Reserved 11b: Reserved 216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM Mode Register Definition 09005aef85eb530a 216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN 38 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. |
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