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EDB8164B4PR-1DATF-R 数据表(PDF) 63 Page - Micron Technology

部件名 EDB8164B4PR-1DATF-R
功能描述  216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM Features
PDF  152 Pages
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制造商  MICRON [Micron Technology]
网页  http://www.micron.com
标志 MICRON - Micron Technology

EDB8164B4PR-1DATF-R 数据表(HTML) 63 Page - Micron Technology

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Figure 40: WRITE Burst with Auto Precharge – WL = 1, BL = 4
Bankn
col addr
Col addr
WRITE
NOP
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK_c
CK_t
CA[9:0]
CMD
DQS_c
DQS_t
DQ
WL = 1
tWR
Transitioning data
NOP
NOP
NOP
NOP
NOP
D
IN A0
D
IN A1
D
IN A2
D
IN A3
ACTIVATE
NOP
Bankn
row addr
Row addr
≥tRPpb
Table 48: PRECHARGE and Auto Precharge Clarification
From
Command
To Command
Minimum Delay Between Commands
Unit
Notes
READ
PRECHARGE to same bank as READ
BL/2 + MAX(2, RU(tRTP/tCK)) - 2
CLK
1
PRECHARGE ALL
BL/2 + MAX(2, RU(tRTP/tCK)) - 2
CLK
1
BST
PRECHARGE to same bank as READ
1
CLK
1
PRECHARGE ALL
1
CLK
1
READ w/AP
PRECHARGE to same bank as READ w/AP
BL/2 + MAX(2, RU(tRTP/tCK)) - 2
CLK
1, 2
PRECHARGE ALL
BL/2 + MAX(2, RU(tRTP/tCK)) - 2
CLK
1
ACTIVATE to same bank as READ w/AP
BL/2 + MAX(2, RU(tRTP/tCK)) - 2 + RU(tRPpb/
tCK)
CLK
1
WRITE or WRITE w/AP (same bank)
Illegal
CLK
3
WRITE or WRITE w/AP (different bank)
RL + BL/2 + RU(tDQSCKmax/tCK) - WL + 1
CLK
3
READ or READ w/AP (same bank)
Illegal
CLK
3
READ or READ w/AP (different bank)
BL/2
CLK
3
WRITE
PRECHARGE to same bank as WRITE
WL + BL/2 + RU(tWR/tCK) + 1
CLK
1
PRECHARGE ALL
WL + BL/2 + RU(tWR/tCK) + 1
CLK
1
BST
PRECHARGE to same bank as WRITE
WL + RU(tWR/tCK) + 1
CLK
1
PRECHARGE ALL
WL + RU(tWR/tCK) + 1
CLK
1
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
PRECHARGE Command
09005aef85eb530a
216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN
63
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.



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