EDB8164B4PR-1DATF-R datasheet(75/152 Pages) MICRON

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Partial-Array Self Refresh – Bank Masking

Any device of densities of 64Mb–512Mb is comprised of four banks; a device of 1Gb

density or higher is comprised of eight banks. Each bank can be configured independ-

ently whether or not a SELF REFRESH operation will occur in that bank. One 8-bit

mode register (accessible via the MRW command) is assigned to program the bank-

masking status of each bank up to eight banks. For bank masking bit assignments, see

the MR16 PASR Bank Mask (MA[7:0] = 010h) and MR16 Op-Code Bit Definitions tables.

The mask bit to the bank enables or disables a refresh operation of the entire memory

space within the bank. If a bank is masked using the bank mask register, a REFRESH op-

eration to the entire bank is blocked and bank data retention is not guaranteed in self

refresh mode. To enable a REFRESH operation to a bank, the corresponding bank mask

bit must be programmed as “unmasked.” When a bank mask bit is unmasked, the array

space being refreshed within that bank is determined by the programmed status of the

segment mask bits.

Partial-Array Self Refresh – Segment Masking

Programming segment mask bits is similar to programming bank mask bits. For a den-

sity of 1Gb or higher, eight segments are used for masking (see the MR17 PASR Segment

Mask (MA[7:0] = 011h) and MR17 PASR Segment Mask Definitions tables). A mode reg-

ister is used for programming segment mask bits up to eight bits. For a density of less

than 1Gb, segment masking is not supported.

When the mask bit to an address range (represented as a segment) is programmed as

“masked,” a REFRESH operation to that segment is blocked. Conversely, when a seg-

ment mask bit to an address range is unmasked, refresh to that segment is enabled.

A segment masking scheme can be used in place of or in combination with a bank

masking scheme. Each segment mask bit setting is applied across all banks. For seg-

ment masking bit assignments, see the tables noted above.

Table 50: Bank and Segment Masking Example

Segment Mask (MR17) Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7

Bank Mask (MR16)

100000

Segment 0

0–

–––––

Segment 1

0–

–––––

Segment 2

Segment 3

0–

–––––

Segment 4

0–

–––––

Segment 5

0–

–––––

Segment 6

0–

–––––

Segment 7

Note:

1. This table provides values for an 8-bank device with REFRESH operations masked to

banks 1 and 7, and segments 2 and 7.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

SELF REFRESH Operation

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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