EDB8164B4PR-1DATF-R datasheet(3/152 Pages) MICRON

3 / 152 page

Contents

LPDDR2 Array Configuration ............................................................................................................................ 9

General Notes .............................................................................................................................................. 9

IDD Specifications ........................................................................................................................................... 10

Package Block Diagrams ................................................................................................................................. 16

Package Dimensions ....................................................................................................................................... 18

Ball Assignments ............................................................................................................................................ 21

Ball Descriptions ............................................................................................................................................ 24

Functional Description ................................................................................................................................... 25

Simplified State Diagram ................................................................................................................................ 26

Power-Up and Initialization ............................................................................................................................ 28

Voltage Ramp and Device Initialization ....................................................................................................... 28

Initialization After RESET (Without Voltage Ramp) ...................................................................................... 30

Power-Off Sequence ....................................................................................................................................... 30

Uncontrolled Power-Off Sequence .............................................................................................................. 31

Mode Register Definition ................................................................................................................................ 31

Mode Register Assignments and Definitions ................................................................................................ 31

Commands and Timing .................................................................................................................................. 42

ACTIVATE Command ..................................................................................................................................... 43

8-Bank Device Operation ............................................................................................................................ 44

Read and Write Access Modes ......................................................................................................................... 45

Burst READ Command ................................................................................................................................... 45

READs Interrupted by a READ ..................................................................................................................... 52

Burst WRITE Command .................................................................................................................................. 52

WRITEs Interrupted by a WRITE ................................................................................................................. 55

BURST TERMINATE Command ...................................................................................................................... 55

Write Data Mask ............................................................................................................................................. 57

PRECHARGE Command ................................................................................................................................. 58

READ Burst Followed by PRECHARGE ......................................................................................................... 59

WRITE Burst Followed by PRECHARGE ....................................................................................................... 60

Auto Precharge operation ........................................................................................................................... 61

READ Burst with Auto Precharge ................................................................................................................. 61

WRITE Burst with Auto Precharge ............................................................................................................... 62

REFRESH Command ...................................................................................................................................... 64

REFRESH Requirements ............................................................................................................................. 66

SELF REFRESH Operation ............................................................................................................................... 73

Partial-Array Self Refresh – Bank Masking .................................................................................................... 75

Partial-Array Self Refresh – Segment Masking .............................................................................................. 75

MODE REGISTER READ ................................................................................................................................. 76

Temperature Sensor ................................................................................................................................... 78

DQ Calibration ........................................................................................................................................... 80

MODE REGISTER WRITE Command ............................................................................................................... 82

MRW RESET Command .............................................................................................................................. 82

MRW ZQ Calibration Commands ................................................................................................................ 83

ZQ External Resistor Value, Tolerance, and Capacitive Loading ..................................................................... 85

Power-Down .................................................................................................................................................. 85

Deep Power-Down ......................................................................................................................................... 92

Input Clock Frequency Changes and Stop Events ............................................................................................. 93

Input Clock Frequency Changes and Clock Stop with CKE LOW ................................................................... 93

Input Clock Frequency Changes and Clock Stop with CKE HIGH .................................................................. 94

NO OPERATION Command ............................................................................................................................ 94

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Features

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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