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EDB8164B4PR-1DATF-R 数据表(PDF) 34 Page - Micron Technology

部件名 EDB8164B4PR-1DATF-R
功能描述  216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM Features
PDF  152 Pages
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制造商  MICRON [Micron Technology]
网页  http://www.micron.com
标志 MICRON - Micron Technology

EDB8164B4PR-1DATF-R 数据表(HTML) 34 Page - Micron Technology

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Table 16: MR1 Op-Code Bit Definitions (Continued)
Feature
Type
OP
Definition
Notes
BT = burst type
Write-only
OP3
0b: Sequential (default)
1b: Interleaved
WC = wrap control
Write-only
OP4
0b: Wrap (default)
1b: No wrap (allowed for BL4 only)
nWR = number of tWR clock
cycles
Write-only
OP[7:5]
001b: nWR = 3 (default)
2
010b: nWR = 4
011b: nWR = 5
100b: nWR = 6
101b: nWR = 7
110b: nWR = 8
All others: Reserved
Notes:
1. BL16, interleaved is not an official combination to be supported.
2. The programmed value in nWR register is the number of clock cycles that determines
when to start internal precharge operation for a WRITE burst with AP enabled. It is de-
termined by RU (tWR/tCK).
Table 17: Burst Sequence by Burst Length (BL), Burst Type (BT), and Wrap Control (WC)
Notes 1–5 apply to all parameters and conditions
BL
BT
C3
C2
C1
C0
WC
Burst Cycle Number and Burst Address Sequence
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
4
Any
X
X
0b
0b
Wrap
0123
X
X
1b
0b
2301
Any
X
X
X
0b
No
wrap
yy +
1
y +
2
y +
3
8
Seq
X
0b
0b
0b
Wrap
01234567
X
0b
1b
0b
23456701
X
1b
0b
0b
45670123
X
1b
1b
0b
67012345
Int
X
0b
0b
0b
01234567
X
0b
1b
0b
23016745
X
1b
0b
0b
45670123
X
1b
1b
0b
67452301
Any
X
X
X
0b
No
wrap
Illegal (not supported)
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Mode Register Definition
09005aef85eb530a
216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN
34
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.



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