EDB8164B4PR-1DATF-R datasheet(76/152 Pages) MICRON

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MODE REGISTER READ

The MODE REGISTER READ (MRR) command is used to read configuration and status

data from SDRAM mode registers. The MRR command is initiated with CS_n LOW, CA0

LOW, CA1 LOW, CA2 LOW, and CA3 HIGH at the rising edge of the clock. The mode reg-

ister is selected by CA1f–CA0f and CA9r–CA4r. The mode register contents are available

on the first data beat of DQ[7:0] after RL × tCK + tDQSCK + tDQSQ and following the ris-

ing edge of the clock where MRR is issued. Subsequent data beats contain valid but un-

defined content, except in the case of the DQ calibration function, where subsequent

data beats contain valid content as described in the Data Calibration Pattern Descrip-

tion table. All DQS_t,DQS_c are toggled for the duration of the mode register READ

burst.

The MRR command has a burst length of four. MRR operation (consisting of the MRR

command and the corresponding data traffic) must not be interrupted. The MRR com-

mand period (tMRR) is two clock cycles. The MRR command issued to reserved and

write-only registers should returns valid but undefined content on all data beats, and

DQS_t, DQS_c should be toggled.

Figure 49: MRR Timing – RL = 3, tMRR = 2

MRR1

NOP2

CK_c

CK_t

CA[9:0]

CMD

DQS_c

DQS_t

DQ[7:0]3

RL = 3

MRR1

Valid

tMRR = 2

DQ[MAX:8]

OUT B

OUT A

Transitioning data

Undefined

Notes:

1. MRRs to DQ calibration registers MR32 and MR40 are described in the Data Calibration

Pattern Description table.

2. Only the NOP command is supported during tMRR.

3. Mode register data is valid only on DQ[7:0] on the first beat. Subsequent beats contain

valid but undefined data. DQ[MAX:8] contain valid but undefined data for the duration

of the MRR burst.

4. Minimum MRR to write latency is RL + RU(tDQSCKmax/tCK) + 4/2 + 1 - WL clock cycles.

5. Minimum MRR to MRW latency is RL + RU(tDQSCKmax/tCK) + 4/2 + 1 clock cycles.

READ bursts and WRITE bursts cannot be truncated by MRR. Following a READ com-

mand, the MRR command must not be issued before BL/2 clock cycles have completed.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

MODE REGISTER READ

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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