EDB8164B4PR-1DATF-R datasheet(85/152 Pages) MICRON

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2. CKE must be registered HIGH continuously during the calibration period.

3. All devices connected to the DQ bus should be High-Z during the calibration process.

ZQ External Resistor Value, Tolerance, and Capacitive Loading

To use the ZQ calibration function, a 240 ohm (±1% tolerance) external resistor must be

connected between the ZQ pin and ground. A single resistor can be used for each device

or one resistor can be shared between multiple devices if the ZQ calibration timings for

each device do not overlap. The total capacitive loading on the ZQ pin must be limited

(see the Input/Output Capacitance table).

Power-Down

Power-down is entered synchronously when CKE is registered LOW and CS_n is HIGH

at the rising edge of clock. A NOP command must be driven in the clock cycle following

power-down entry. CKE must not go LOW while MRR, MRW, READ, or WRITE opera-

tions are in progress. CKE can go LOW while any other operation such as ACTIVATE,

PRECHARGE, auto precharge, or REFRESH are in progress, but the power-down IDD

specification will not be applied until such operations are complete.

If power-down occurs when all banks are idle, this mode is referred to as idle power-

down; if power-down occurs when there is a row active in any bank, this mode is refer-

red to as active power-down.

Entering power-down deactivates the input and output buffers, excluding CK_t, CK_c,

and CKE. In power-down mode, CKE must be held LOW; all other input signals are

“Don’t Care.” CKE LOW must be maintained until tCKE is satisfied. VREFCA must be

maintained at a valid level during power-down.

VDDQ can be turned off during power-down. If VDDQ is turned off, VREFDQ must also be

turned off. Prior to exiting power-down, both VDDQ and VREFDQ must be within their re-

spective minimum/maximum operating ranges (see AC and DC Operating Conditions).

No refresh operations are performed in power-down mode. The maximum duration in

power-down mode is limited only by the refresh requirements outlined in REFRESH

Command.

The power-down state is exited when CKE is registered HIGH. The controller must drive

CS_n HIGH in conjunction with CKE HIGH when exiting the power-down state. CKE

HIGH must be maintained until tCKE is satisfied. A valid, executable command can be

applied with power-down exit latency tXP after CKE goes HIGH. Power-down exit laten-

cy is defined in the AC Timing section.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Power-Down

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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