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EDB8164B4PR-1DATF-R 数据表(PDF) 132 Page - Micron Technology |
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EDB8164B4PR-1DATF-R 数据表(HTML) 132 Page - Micron Technology |
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132 / 152 page  Table 91: AC Timing (Continued) Notes 1–2 apply to all parameters and conditions. AC timing parameters must satisfy the tCK minimum conditions (in mul- tiples of tCK) as well as the timing specifications when values for both are indicated. Parameter Symbol Min/ Max tCK Min Data Rate Unit Notes 1066 933 800 667 533 400 333 Maximum clock jitter between two consectuive clock cycles (with allowed jitter) tJIT(cc), allowed MAX – 180 190 200 220 240 280 300 ps Duty cycle jitter (with allowed jitter) tJIT(duty), allowed MIN – MIN ((tCH(abs),min - tCH(avg),min), (tCL(abs),min - tCL(avg),min)) × tCK(avg) ps MAX – MAX ((tCH(abs),max - tCH(avg),max), (tCL(abs),max - tCL(avg),max)) × tCK(avg) Cumulative errors across 2 cycles tERR(2per), allowed MIN – -132 -140 -147 -162 -177 -206 -221 ps MAX – 132 140 147 162 177 206 221 Cumulative errors across 3 cycles tERR(3per), allowed MIN – -157 -166 -175 -192 -210 -245 -262 ps MAX – 157 166 175 192 210 245 262 Cumulative errors across 4 cycles tERR(4per), allowed MIN – -175 -185 -194 -214 -233 -272 -291 ps MAX – 175 185 194 214 233 272 291 Cumulative errors across 5 cycles tERR(5per), allowed MIN – -188 -199 -209 -230 -251 -293 -314 ps MAX – 188 199 209 230 251 293 314 Cumulative errors across 6 cycles tERR(6per), allowed MIN – -200 -211 -222 -244 -266 -311 -333 ps MAX – 200 211 222 244 266 311 333 Cumulative errors across 7 cycles tERR(7per), allowed MIN – -209 -221 -232 -256 -279 -325 -348 ps MAX – 209 221 232 256 279 325 348 Cumulative errors across 8 cycles tERR(8per), allowed MIN – -217 -229 -241 -266 -290 -338 -362 ps MAX – 217 229 241 266 290 338 362 Cumulative errors across 9 cycles tERR(9per), allowed MIN – -224 -237 -249 -274 -299 -349 -374 ps MAX – 224 237 249 274 299 349 374 Cumulative errors across 10 cycles tERR(10per), allowed MIN – -231 -244 -257 -282 -308 -359 -385 ps MAX – 231 244 257 282 308 359 385 Cumulative errors across 11 cycles tERR(11per), allowed MIN – -237 -250 -263 -289 -316 -368 -395 ps MAX – 237 250 263 289 316 368 395 Cumulative errors across 12 cycles tERR(12per), allowed MIN – -242 -256 -269 -296 -323 -377 -403 ps MAX – 242 256 269 296 323 377 403 Cumulative errors across n = 13, 14, 15…, 49, 50 cycles tERR(nper), allowed MIN tERR(nper),allowed,min = (1 + 0.68ln(n)) × tJIT(per),allowed,min ps MAX tERR(nper), allowed,max = (1 + 0.68ln(n)) × tJIT(per),allowed,max ZQ Calibration Parameters Initialization calibration time tZQINIT MIN – 1 1 1 1 1 1 1 μs Long calibration time tZQCL MIN 6 360 360 360 360 360 360 360 ns Short calibration time tZQCS MIN 6 90 90 90 90 90 90 90 ns 216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM AC Timing 09005aef85eb530a 216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN 132 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. |
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