STM32WLE4JC datasheet(45/146 Pages) STMICROELECTRONICS

45 / 146 page

DS13105 Rev 9

45/146

STM32WLE5/E4xx

Functional overview

3.25.6

SysTick timer

This timer is dedicated to real-time operating systems, but can also be used as a standard

down counter.

SysTick timer main features:

•

24-bit down counter

•

autoreload capability

•

maskable system interrupt generation when the counter reaches 0

•

programmable clock source

3.26

Real-time clock (RTC), tamper and backup registers

The RTC is an independent BCD timer/counter. The RTC provides a time-of-day

clock/calendar with programmable alarm interrupts.

As long as the supply voltage remains in the operating range, the RTC never stops,

regardless of the device status (Run mode, low-power mode or under reset).

The RTC provides an automatic wakeup to manage all low-power modes.

The RTC is functional in VBAT mode.

Twenty 32-bit backup registers are retained in all low-power modes and also in VBAT mode.

These registers can be used to store sensitive data as their content is protected by a tamper

detection circuit.

Three tamper pins and four internal tampers are available for anti-tamper detection. The

external tamper pins can be configured for edge or level detection with or without filtering.

3.27

Inter-integrated circuit interface (I2C)

The device embeds three I2Cs, with features implementation listed in the he table below.

The I2C bus interface handles communications between the microcontroller and the serial

I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.

The I2C peripheral supports:

•

I2C bus specification and user manual rev. 5 compatibility:

–

slave and master modes, multimaster capability

–

Standard-mode (Sm), with a bitrate up to 100 Kbit/s

–

Fast-mode (Fm), with a bitrate up to 400 Kbit/s

–

Fast-mode plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os

–

7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

–

programmable setup and hold times

–

clock stretching (optional)

•

SMBus (system management bus) specification rev 2.0 compatibility:

–

hardware PEC (packet error checking) generation and verification with ACK

control

–

address resolution protocol (ARP) support

–

SMBus alert

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