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STM32WLE4JC 数据表(PDF) 29 Page - STMicroelectronics

部件名 STM32WLE4JC
功能描述  Multiprotocol LPWAN 32-bit Arm® Cortex®-M4 MCUs, LoRa®, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
PDF  146 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32WLE4JC 数据表(HTML) 29 Page - STMicroelectronics

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DS13105 Rev 9
29/146
STM32WLE5/E4xx
Functional overview
48
HSI16, depending on the software configuration.
•
Standby mode: VCORE domain is powered off. However, it is possible to preserve the
SRAM2 content as detailed below:
–
Standby mode with SRAM2 retention when the RRS bit is set in the PWR control
register 3 (PWR_CR3). In this case, SRAM2 is supplied by the low-power
regulator.
–
Standby mode when the RRS bit is cleared in the PWR control register 3
(PWR_CR3). In this case the main regulator and the low-power regulator are
powered off.
All clocks in the VCORE domain are stopped. PLL, MSI, HSI16 and HSE32 are disabled.
LSI and LSE can be kept running.
Th RTC can remain active (Standby mode with RTC, Standby mode without RTC). The
sub-GHz radio and the PVD may also remain active when enabled independent from
the CPU. In Standby mode, the PVD selects its lowest level.
The system clock, when exiting Standby modes, is MSI at 4 MHz.
•
Shutdown mode: VCORE domain is powered off. All clocks in the VCORE domain are
stopped. PLL, MSI, HSI16, LSI and HSE32 are disabled. LSE can be kept running. The
system clock when exiting the Shutdown mode, is MSI at 4 MHz. In this mode, the
supply voltage monitoring is disabled and the product behavior is not guaranteed in
case of a power voltage drop.
The table below summarizes the peripheral features over all available modes. Wakeup
capability is detailed in gray cells.
Table 7. Functionalities depending on system operating mode(1)
Peripheral
Stop 0
Stop 1
Stop 2
Standby Shutdown
-
-
-
-
-
CPU
Y
R
Y
R
R
-R
-R
--
--
--
Sub-GHz radio system
O
O
O
O
O
OO
OO
OO
O-
--
Flash memory
(up to 256 Kbytes)
YO(2) O(3)
O(2)
(3)
R
-R
-R
-R
-R
-R
Flash memory interface
Y
Y
Y
Y
R
-R
-R
--
--
--
SRAM1
Y
O(2)
YO(2)
R
-R
-R
--
--
--
SRAM2
Y
O(2)
YO(2)
R
-R
-R
-O(4)
--
--
Backup registers
Y
Y
Y
Y
R
-R
-R
-R
-R
-R
Brownout reset (BOR)
Y
Y
Y
Y
Y
YY
YY
YY
Y-
--
Programmable voltage
detector (PVD)
OO
O
O
O
OO
OO
OO(5) O(5)
-
--
Peripheral voltage monitor
(PVM3)
OO
O
O
O
OO
OO
O-
--
--



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