STM32WLE4JC datasheet(21/146 Pages) STMICROELECTRONICS

21 / 146 page

DS13105 Rev 9

21/146

STM32WLE5/E4xx

Functional overview

Figure 4. Low output power PA

3.8.4

Receiver

The receive chain comprises a differential low-noise amplifier (LNA), a down-converter to

low-IF by mixer operation in quadrature configuration. The I and Q signals are low pass

filtered and a Ʃ∆ ADC converts them into the digital domain. In the digital modem, the

signals are decimated, further down converted and channel filtered. The demodulation is

done according to the selected modulation scheme.

The down mixing to low-IF is done by mixing the receive signal with the local RF-PLL

located in the negative frequency, where -flo = -frf + -fif. (where flo is the local RF-PLL

frequency, frf is the received signal and fif is the intermediate frequency). The wanted signal

is located at frf = flo + fif.

The receiver features automatic I and Q calibration, that improves image rejection. The

calibration is done automatically at startup before using the receiver, and can be requested

by command.

The receiver supports LoRa, (G)MSK and (G)FSK modulations. The received packet

payload size depends on the modulation scheme.

3.8.5

RF-PLL

The RF-PLL is used as the frequency synthesizer for the generation of the local oscillator

frequency (flo) for both transmit and receive chains. The RF-PLL uses auto calibration and

uses the 32 MHz HSE32 reference. The sub-GHz radio covers all continuous frequencies in

the range between 150 to 960 MHz.

MSv62617V2

Note: Use of the SMPS is optional. When SMPS is not used, the BOM can be reduced by removing the coil

between VLXSMPS and VFBSMPS pins.

VLXSMPS

VFBSMPS (1.55V)

VDDPA

VR_PA (up to 1.35V)

RFO_LP

LDO/SMPS

REG

LP PA

LDO mode

SMPS mode

VDDSMPS (1.8 to 3.6V)

VDD

VLXSMPS

VFBSMPS (1.55V)

VDDPA

VR_PA (up to 1.35V)

RFO_LP

LDO/SMPS

REG

VDD

LP PA

VDDSMPS (1.8 to 3.6V)

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