STM32WLE4JC datasheet(11/146 Pages) STMICROELECTRONICS

11 / 146 page

DS13105 Rev 9

11/146

STM32WLE5/E4xx

Introduction

This document provides information on the STM32WLE5/E4xx microcontrollers.

For information on the device errata with respect to the datasheet and reference manual,

refer to the STM32WLE5/E4xx errata sheet (ES0506), available on the STMicroelectronics

website www.st.com.

For information on the Arm®(a) Cortex®-M4 core, refer to the Cortex®-M4 Technical

Reference Manual available from the www.arm.com website.

For information on LoRa® modulation, refer to the Semtech website

(https://www.semtech.com/technology/lora).

Description

The STM32WLE5/E4xx long-range wireless and ultra-low-power devices embed a powerful

and ultra-low-power LPWAN-compliant radio solution, enabling the following modulations:

LoRa®, (G)FSK, (G)MSK, and BPSK.

The LoRa® modulation is available in STM32WLx5xx only.

These devices are designed to be extremely low-power and are based on the

high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to

48 MHz. This core implements a full set of DSP instructions and an independent memory

protection unit (MPU) that enhances the application security.

The devices embed high-speed memories (Flash memory up to 256 Kbytes, SRAM up to

64 Kbytes), and an extensive range of enhanced I/Os and peripherals.

The devices also embed several protection mechanisms for embedded Flash memory and

SRAM: readout protection, write protection and proprietary code readout protection.

These devices offer a 12-bit ADC, a 12-bit DAC low-power sample-and-hold, two

ultra-low-power comparators associated with a high-accuracy reference voltage generator.

The devices embed a low-power RTC with a 32-bit sub-second wakeup counter, one 16-bit

single-channel timer, two 16-bit four-channel timers (supporting motor control), one 32-bit

four-channel timer and three 16-bit ultra-low-power timers.

These devices also embed two DMA controllers (7 channels each) allowing any transfer

combination between memory (Flash memory, SRAM1 and SRAM2) and peripheral, using

the DMAMUX1 for flexible DMA channel mapping.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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