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PCF8536AT 数据表(PDF) 50 Page - NXP Semiconductors

部件名 PCF8536AT
功能描述  Automotive 102 x 4 Chip-On-Glass LCD segment driver
PDF  103 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

PCF8536AT 数据表(HTML) 50 Page - NXP Semiconductors

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PCA8530
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2 — 25 September 2014
50 of 103
NXP Semiconductors
PCA8530
Automotive 102 x 4 Chip-On-Glass LCD segment driver
8.11 Backplane outputs
The LCD drive section includes 4 backplane outputs: COM0 to COM3. The backplanes
are double implemented to offer a higher flexibility for the glass layout.
The backplane output signals are generated based on the selected LCD multiplex drive
mode. Table 36 describes which outputs are active for each of the multiplex drive modes
and what signal is generated.
Table 37 describes the corresponding layout topology.
8.11.1 Driving strength on the backplanes
Corresponding output pins (COMx), which are carrying the same signal (BPx), may
optionally be connected to the display. This allows gaining a higher driving strength. If not
required, the unused pins can be left open-circuit.
8.12 Segment outputs
The LCD drive section includes 102 segment outputs (S0 to S101) which must be
connected directly to the LCD. The segment output signals are generated based on the
multiplexed backplane signals and with data resident in the display register. When less
than 102 segment outputs are required, the unused segment outputs must be left
open-circuit.
8.13 Display register
The display register holds the display data while the corresponding multiplex signals are
generated.
Table 36.
Mapping of output pins and corresponding output signals with respect to the
multiplex driving mode
Multiplex
drive mode
Output pin
COM0
COM1
COM2
COM3
Signal
static
BP0
BP0
BP0
BP0
1:2
BP0
BP1
BP0
BP1
1:4
BP0
BP1
BP2
BP3
Table 37.
Layout topology of output pins and corresponding output signals with respect to
the multiplex driving mode
Multiplex drive mode
Static
1:2
1:4
Signal
On pin
Signal
On pin
Signal
On pin
BP0
COM0
BP0
COM0
BP0
COM0
COM1
COM2
BP1
COM1
COM2
BP1
COM1
BP2
COM2
COM3
COM3
BP3
COM3



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