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PCF8536AT 数据表(PDF) 6 Page - NXP Semiconductors

部件名 PCF8536AT
功能描述  Automotive 102 x 4 Chip-On-Glass LCD segment driver
PDF  103 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

PCF8536AT 数据表(HTML) 6 Page - NXP Semiconductors

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PCA8530
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2 — 25 September 2014
6 of 103
NXP Semiconductors
PCA8530
Automotive 102 x 4 Chip-On-Glass LCD segment driver
7.2 Pin description
Table 4.
Pin description
Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified.
Symbol
Pin
Type
Description
Backplane output pins
COM3
1 to 7, 190 to 195
output
LCD backplane
COM2
8 to 11, 186 to 189
COM1
117 to 120, 182 to 185
COM0
121 to 125, 178 to 181
Segment output pins
S101
126, 127
output
LCD segment
S100 to S51
128 to 177
S50 to S1
196 to 245
S0
246, 247
VLCD pins
VLCDIN
12 to 15
supply
VLCD input
VLCDSENSE
16 to 18
input
VLCD regulation input
VLCDOUT
19 to 22
output
VLCD output
Test pins
T4
23 to 25
output
not accessible; must be left open
T3
26 to 30
input
not accessible; must be connected to T5
T5
31, 32
output
not accessible; must be connected to T3
T6
33, 34
output
not accessible; must be left open
T1
58, 59
input
not accessible; must be connected to VSS1
T2
60, 61
Supply pins
VSS2[1]
35 to 44
supply
ground supply
VSS3[1]
45 to 48
VSS1[1]
49 to 57
VDD1
74 to 78
supply
supply voltage 1 (analog and digital)
VDD3
79 to 82
supply
supply voltage 3 (analog)
VDD2
83 to 90
supply
supply voltage 2 (charge pump)
Oscillator, synchronization, addressing, and reset pins
CLK[2]
93 to 95
input/output
internal oscillator output, external oscillator input
OSC[2]
68, 69
input
clock (internal/external) selector
SYNC1[3]
96 to 98
input/output
charge pump synchronization for cascaded devices; must not be
connected if VLCD is externally supplied
SYNC0[3]
99 to 101
input/output
display synchronization for cascaded devices
RST
102, 103
input
active LOW reset input
A0
62, 63
input
hardware device address selection for cascading;
connect to VSS1 for logic 0
connect to VDD1 for logic 1
A1
64, 65
input



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