PCF8536AT datasheet(61/103 Pages) NXP

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PCA8530

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Product data sheet

Rev. 2 — 25 September 2014

61 of 103

NXP Semiconductors

PCA8530

Automotive 102 x 4 Chip-On-Glass LCD segment driver

9.3 SPI interface

The SPI interface is selected by connecting pin IFS to VSS1.

Data transfer to the device is made via a four-line SPI-bus (see Table 45). The SPI-bus is

initialized whenever the chip enable line pin CE is LOW.

[1]

The chip enable must not be wired permanently LOW.

9.3.1 Data transmission

The chip enable signal (CE) is used to initialize data transmission. Each data transfer is a

byte, with the MSB sent first. The first byte transmitted is the subaddress byte.

The subaddress byte opens the communication with a read/write bit and a subaddress.

The subaddress is used to identify multiple devices on one SPI bus.

Figure 40 shows an example of an SPI data transfer.

Table 45.

Serial interface

Symbol

Function

Description

chip enable input;

active LOW[1]

when HIGH, the interface is reset

SCL

serial clock input

input may be higher than VDD1

SDI/SDAIN serial data input

input may be higher than VDD1;

input data is sampled on the rising edge of SCL

SDO

serial data output

Fig 39. SPI-bus protocol - data transfer overview

Table 46.

Subaddress byte definition

Bit

Symbol

Value

Description

7R/W

data read or write selection

write data

read data

6to5

subaddress; other codes cause the device to

ignore data transfer

4to0

unused

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