PCF8536AT datasheet(58/103 Pages) NXP

58 / 103 page

PCA8530

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Product data sheet

Rev. 2 — 25 September 2014

58 of 103

NXP Semiconductors

PCA8530

Automotive 102 x 4 Chip-On-Glass LCD segment driver

A LOW-to-HIGH change of the data line while the clock is HIGH is defined as the STOP

condition (P).

The START and STOP conditions are shown in Figure 34.

9.2.3 System configuration

A device generating a message is a transmitter; a device receiving a message is the

receiver. The device that controls the message is the master; and the devices which are

controlled by the master are the slaves. The system configuration is shown in Figure 35.

9.2.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge

cycle.

• A slave receiver which is addressed must generate an acknowledge after the

reception of each byte.

• Also a master receiver must generate an acknowledge after the reception of each

byte that has been clocked out of the slave transmitter.

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be considered).

• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgement on the I2C-bus is shown in Figure 36.

Fig 34. I2C-bus - definition of START and STOP conditions

Fig 35. I2C-bus - system configuration

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